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参数资料
| 型号： | TPS54550PWPRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 6/31页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 16HTSSOP |
| 产品培训模块： | Understanding SWIFT Step Down Dc/Dc Converters |
| 标准包装： | 2,000 |
| 系列： | SWIFT™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.9 V ~ 12 V |
| 输入电压： | 4.5 V ~ 20 V |
| 频率 - 开关： | 250kHz，500kHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-HTSSOP |
| 配用： | 296-19743-ND - EVALUATION MODULE FOR TPS54550 |
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SLVS623A – MARCH 2006 – REVISED APRIL 2006
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
www.ti.com
VIN
VIN
UVLO
1
2
3
16
15
14
BOOT
PH
PH
PWRGD
RT
SYNC
SSENA
COMP
4
5
6
7
8
THERMAL
PAD
(17)
13
12
11
10
9
LSG
VBIAS
PGND
AGND
VSENSE
TERMINAL
NO. NAME
NOTE:
If there is not a Pin 1 indicator, turn device to enable
reading the symbol from left to right. Pin 1 is at the lower
left corner of the device.
Terminal Functions
DESCRIPTION
6
1, 2
3
4
5
6
7
8
9
10
11
12
13
14, 15
16
17
VIN
UVLO
PWRGD
RT
SYNC
SSENA
COMP
VSENSE
AGND
PGND
VBIAS
LSG
PH
BOOT
PowerPAD
Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10- μ F ceramic capacitor.
Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the
internal default VIN start and stop thresholds.
Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output
voltage. There is an internal rising edge filter on the output of the PWRGD comparator.
Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin
to ground or floating will set the frequency to an internally preselected frequency.
Bidirectional synchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The
output is a falling edge signal out of phase with the rising edge of PH. SYNC may be used as an input to
synchronize to a system clock by connecting to a falling edge signal when an RT resistor is used. See 180
Slow Start/Enable. The SSENA pin is a dual function pin which provides a logic enable/disable and a slow start
time set. Below 0.5 V, the device stops switching. Float pin to enable. Capacitor to ground adjusts the slow start
time. See Extending Slow Start Time section.
Error amplifier output. Connect frequency compensation network from COMP to VSENSE pins.
Inverting node error amplifier.
Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD.
Power Ground—Noisy internal ground. Return currents from the LSG driver output return through the PGND pin.
Connect to AGND and PowerPAD.
Internal 8.0 V bias voltage. A 1.0 μ F ceramic bypass capacitance is required on the VBIAS pin.
Gate drive for low-side MOSFET. Connect gate of n-channel MOSFET.
Phase node—Connect to external L-C filter.
Bootstrap for high-side gate driver. Connect 24 ? and 0.1 μ F ceramic capacitor from BOOT to PH pins.
PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 26 for an example
PCB layout.
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