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参数资料
| 型号： | TPS65072TRSLRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48 |
| 文件页数： | 49/90页 |
| 文件大小： | 1375K |
| 代理商： | TPS65072TRSLRQ1 |
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SLVSAP7 – JANUARY 2011
CON_CTRL1. Register Address: 0Dh
CON_CTRL1
B7
B6
B5
B4
B3
B2
B1
BO
DCDC1
DCDC2
DCDC3
LDO1
LDO2
Bit name and function
DCDC_SQ2
DCDC_SQ1
DCDC_SQ0
ENABLE
Default for
1
–70, –72, -73, -732
See Table 9
1
0
for TPS65731 only
DCDC1_E
DCDC2_EN DCDC3_EN
Set by signal
LDO_ENZ
NZ
Z
Default value loaded by:
UVLO
Read/write
R/W
The CON_CTRL1 register can be used to disable and enable all power supplies via the serial interface. Default
is to allow all supplies to be on, providing the relevant enable pin is high. The following tables indicate how the
enable pins and the CON_CTRL1 register are combined. The CON_CTRL1 Bits are automatically reset to
default when the corresponding enable pin is low.
Bit 7..5
DCDC_SQ2 to DCDC_SQ0: power-up sequencing (power down sequencing is the reverse)
000 = power-up sequencing is: DCDC2 only; DCDC1 and DCDC3 are not part of the automatic
sequencing and are enabled by their enable pins EN_DCDC1 and EN_DCDC3
001 = power-up sequencing is DCDC2 and DCDC3 at the same time, DCDC1 is not part of the
automatic sequencing and is enabled by its enable pin EN_DCDC1
010 = power-up sequencing is: DCDC1 when power good then DCDC2 and DCDC3 at the same time
011 = power-up sequencing is: DCDC3 when power good then DCDC2; DCDC1 is not part of the
automatic sequencing and is controlled by its EN_DCDC1 pin.
100 = power-up sequencing is: DCDC3 is started at the same time with LDO2 if Bit
MASK_EN_DCDC3 in register 0Eh is set (default is set). DCDC1 and DCDC2 are started at the same
time when LDO2 is PGOOD (defined in LDO sequencing 111); DCDC3 is enabled or disabled with its
EN_DCDC3 pin if MASK_EN_DCDC3 in register 0Eh is cleared (set =0). (Sirf PRIMA, start-up from
OFF or start-up after SLEEP)
101 = DCDC converters are enabled individually with the external enable pins
110 = DCDC1first, when power good then DCDC2, when power good then DCDC3
111 = power-up sequencing is: DCDC1 and DCDC2 at the same time >1ms after LDO2 has been
started (defined in LDO sequencing 010); DCDC3 is not part of the automatic sequencing but is
enabled with its EN_DCDC3 pin (Atlas4)
In case of automatic sequencing other than 101, the start is initiated by going into ON-state. DCDC converters
that are not part of the automatic sequencing can be enabled by pulling their enable pin to a logic HIGH level at
any time in ON-state. The enable pins for the converters that are automatically enabled, should be tied to GND.
For sequencing option DCDC_SEQ=111, the start is initiated by going into ON-state, however, the external LDO
connected to pin EN_EXTLDO is powered first, followed by LDO2.
(The sequencing of LDO1 and LDO2 is defined in register LDO_CTRL1)
Copyright 2011, Texas Instruments Incorporated
53
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