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参数资料
| 型号： | TPS65072TRSLRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 6 X 6 MM, 0.4 MM PITCH, PLASTIC, QFN-48 |
| 文件页数： | 52/90页 |
| 文件大小： | 1375K |
| 代理商： | TPS65072TRSLRQ1 |
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SLVSAP7 – JANUARY 2011
www.ti.com
CON_CTRL3. Register Address: 0Fh
CON_CTRL3
B7
B6
B5
B4
B3
B2
B1
BO
FPWM
DCDC1
DCDC2
DCDC3
LDO1
LDO2
Bit name and function
DCDC3
DCDC2
DCDC1
discharge
Default value loaded by:
UVLO
Read/write
R/W
Bit 7
FPWM DCDC3:
0 = DCDC3 converter operates in PWM / PFM mode
1 = DCDC3 converter is forced into fixed frequency PWM mode
Bit 6
FPWM DCDC2:
0 = DCDC2 converter operates in PWM / PFM mode
1 = DCDC2 converter is forced into fixed frequency PWM mode
Bit 5
FPWM DCDC1:
0 = DCDC1 converter operates in PWM / PFM mode
1 = DCDC1 converter is forced into fixed frequency PWM mode
Bit 4–0
0 = the output capacitor of the associated converter or LDO is not actively discharged when
the converter or LDO is disabled
1 = the output capacitor of the associated converter or LDO is actively discharged when the
converter or LDO is disabled. This decreases the fall time of the output voltage at light load
DEFDCDC1. Register Address: 10h
DEFDCDC1
B7
B6
B5
B4
B3
B2
B1
BO
DCDC1
Bit name and function
DCDC1[5]
DCDC1[4]
DCDC1[3]
DCDC1[2]
DCDC1[1]
DCDC1[0]
extadj
Default value loaded by:
UVLO
Read/write
R/W
R
R/W
DEFDCDC1 sets the output voltage for the DCDC1 converter. Per default the converter is internally fixed but can
be programmed to an externally adjustable version by setting Bit 7 (Ext adj). The default setting is defined in an
EEPROM Bit. In case the externally adjustable version is programmed, the external resistor divider need to be
connected to the VDCDC1 pin, otherwise this pin needs to be connected to the output voltage directly. For the
fixed voltage version, the output voltage is set with Bits B0 to B5 (DCDC1[5] to DCDC1[0]):
All step-down converters provide the same output voltage range, see details under DEFDCDC3
56
Copyright 2011, Texas Instruments Incorporated
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