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参数资料
| 型号： | TSB14AA1 |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 电机及电子学工程师联合会1394-1995。 3.3。 1-port.50/100Mbps。底板PHY |
| 文件页数： | 28/35页 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1 |
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6
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8
6.2.4
Backplane Transmit Data Timing
Edge separation is the minimum required time between any two consecutive transitions of the backplane bus signals,
as they appear from the output of the transmitters, whether they are transitions on the same signal or transitions on
the two separate signals. A minimum edge separation is required to ensure proper operation of the data strobe
bit-level encoding mechanism. TDATA and TSTRB have the relationship shown in Figure 6
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7 and Table 6
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10.
t(2)
t(2)
t(1)
TDATA
TSTRB
t(2)
t(2)
t(1)
t(1)
t(1)
Figure 6
–
7. Minimum Edge Separation
Table 6
–
10. TSB14AA1A to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t(1)
t(2)
This parameter is based on a maximum total transmit skew of 2 ns.
Bit cell period for data
9.44 ns minimum
19.44 ns minimum
Transmit (Tx) edge separation
8.65 ns minimum
18.65 ns minimum
6.2.5
Backplane Receive Data Timing
The receiver typically uses the transitions on the incoming bus signals RDATA and RSTRB to derive a clock at the
code bit frequency to extract the NRZ signal on RDATA. This clock can be derived by performing an exclusive-OR
(XOR) of RDATA and RSTRB.
The bus signals, as they appear from the backplane transceiver media and into the receiver, should fall within the
timing constraints outlined by Figure 6
–
8.
RDATA
RSTRB
t(3)
t(1)
t(1)
t(1)
t(1)
t(2)
t(3)
t(2)
Figure 6
–
8. Backplane Receive Data Timing
Table 6
–
11. TSB14AA1A to Backplane Transceiver Timing
PARAMETER
98.304 MHz
49.152 MHz
t(1)
t(2)
t(3)
This parameter is based on a maximum total transmit skew of 2 ns and a maximum backplane skew of 0.5 ns.
This assumes total receive skew is less than receive edge separation (i.e., some skew margin exists).
Bit cell period
10.1715 ns nominal
20.34 nominal
Receive (Rx) edge separation
3.4 ns minimum
16.3 ns maximum
3.4 ns minimum
36.6 ns maximum
相关PDF资料 |
PDF描述 |
|---|---|
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB14AA1A | 制造商:TI 制造商全称:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AI | 制造商:TI 制造商全称:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AIPFB | 功能描述:1394 接口集成电路 IEEE139419953.3V1prt 50/100Mbps BkplnPHY RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB14AA1AIPFBG4 | 功能描述:1394 接口集成电路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB14AA1APFB | 功能描述:1394 接口集成电路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
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