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参数资料
| 型号： | TSB14AA1 |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 电机及电子学工程师联合会1394-1995。 3.3。 1-port.50/100Mbps。底板PHY |
| 文件页数： | 33/35页 |
| 文件大小： | 224K |
| 代理商： | TSB14AA1 |
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6
–
13
A node implementing urgent priority sets its Urgent_Count to three whenever an unlabeled (i.e., fair) packet
is transmitted or received. This includes received packets that are addressed to other nodes.
A node decrements its Urgent_Count whenever a packet with the urgent label is transmitted or received.
This includes received packets that are addressed to other nodes. This ensures that there is at most three
urgent packets for every fair packet. This does not ensure that every node using urgent priority obtains the
bus three times for each fairness interval. The node arbitrating with the highest priority always obtains the
bus before other nodes arbitrating with an urgent, but lower, priority.
In the presence of urgent nodes, a fairness interval ends after the final fair node and up to three remaining urgent
nodes have successfully accessed the bus. Since all fair nodes now have their Arbitration_Enable signals reset and
all urgent nodes have their Urgent_Count decremented to zero, none of the nodes can access the bus. The bus
remains idle until an arbitration reset gap has occurred, re-enabling arbitration on all nodes and starting the next
fairness interval. This process is illustrated in Figure 6
–
11, which illustrates a situation where there are three nodes
arbitrating for the bus with Physical_IDs such that A has the highest priority, B is in the middle priority, and C has the
lowest priority. Nodes A and C are using fair priority and node B is using urgent priority.
Fairness Interval N
Urgent
Packet
Fairness
Interval N+1
arb Node B
arb Node B arb Node B arb Node A
arb Node B arb Node B
arb Node B arb Node C arb Node B
Node B
arb
3
2
1
3
2
1
3
2
1
3
Node B
arb
A
Urgent
Packet
A Node Using The Urgent
Protocol Has a Higher Priority Than Any Fair Node
Fairness
Interval N
–
1
Urgent
Packet
Urgent
Packet
Fair
Packet
Urgent
Packet
Urgent
Packet
Fair
Packet
Urgent
Packet
Urgent
Packet
Urgent
Packet
Arbitration_Enable Set at
Arbitration Reset Gap
Urgent_Count Incremented
by 3 After a Fair Node (A) Wins
Arbitration and Sends a Packet
Urgent_Count Decremented
When Urgent Node Sends a Packet
Urgent_Count Incremented
by 3 After a Fair Node (C) Wins
Arbitration and Sends a Packet
Arbitration_Enable Set at
Arbitration Reset Gap
A
Node A
Arbitration_Enable
Node B
Urgent_Count
Node C
Arbitration_Enable
Urgent_Count Set
to 3 at Arbitration Reset Gap
Note: Physical_ID of A > B > C
Figure 6
–
11. Urgent Arbitration
In the backplane environment, the natural priority is the concatenation of the 4-bit urgent priority level with the
Physical_ID. These results are listed as follows.
A node using the urgent priority always wins an arbitration contest over all nodes using the fair priority.
The node using the highest priority level wins the arbitration level.
When more than one node uses the highest priority level, then the one with the highest Physical_ID wins.
6.4.4
Immediate Arbitration
This arbitration class is used by nodes sending an acknowledge to a received packet. Transmission of the
acknowledge (beginning with a Data_Prefix) occurs as soon as an acknowledge gap is detected. This arbitration
class is referred to as immediate because an arbitration sequence is not transmitted to obtain access to the bus (i.e.,
the node does not actually arbitrate for the bus).
6.5
Reset
6.5.1
Backplane PHY Reset
Upon a power reset event (i.e., power up) registers and control and status registers (CSRs) associated with the
operation of the PHY are initialized to their default values. State machines associated with PHY operations are
initialized. The Bus_Reset signal is not transmitted on the bus by the PHY.
相关PDF资料 |
PDF描述 |
|---|---|
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB14AA1A | 制造商:TI 制造商全称:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AI | 制造商:TI 制造商全称:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB14AA1AIPFB | 功能描述:1394 接口集成电路 IEEE139419953.3V1prt 50/100Mbps BkplnPHY RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB14AA1AIPFBG4 | 功能描述:1394 接口集成电路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB14AA1APFB | 功能描述:1394 接口集成电路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
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