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参数资料
| 型号： | TSB14C01HV |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的电机及电子学工程师联合会1394-1995背板收发器/仲裁者 |
| 文件页数： | 19/35页 |
| 文件大小： | 224K |
| 代理商： | TSB14C01HV |
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5
–
2
–
When the designer must choose a backplane transceiver logic (BTL) transceiver, the FutureBus+
transceiver SN74FB2041A [6] is recommended.
–
When the designer must choose a VERSA module Eurocard (VME) bus transceiver, the VME1395 is
recommended (to be released).
–
When the designer must choose a high speed 5-V transistor-transistor logic (TTL) transceiver, the
SN74BCT756 [7] is recommended.
Refer to application report
TSB12LV01B/TSB14AA1A Reference Schematic
[8]
and application report
TSB14AA1A/Transceivers Reference Schematic [9] for more information.
5.2
Link Selection
The system designer must select links appropriate for the TSB14AA1A and the host interface selected. The following
are requirements for the LLCs needed:
Using the TSB14AA1A at 100 Mbits/s, any 1394 cable link layer can be used.
Using the TSB14AA1A at 50 Mbits/s, it is appropriate to use the TSB12LV01B, TSB12LV32 (GP2Lynx), or
TSB12LV21B (PCILynx), depending on the host-link interface. For example:
–
TSB12LV01B has a 32-bit data bus and is used most appropriately with a host that has 32 or 64-bit data
bus.
–
TSB12LV32 is designed for interface with a Motorola-type microprocessor and should be used for an 8
or 16-bit host.
–
TSB12LV21B is best used if the host is the PCI bus.
It is necessary to verify that the CLK on the PHY-link interface is faster than the CLK on the link-host interface, based
on LPS low time and detecting SCLK.
5.3
Layout Recommendation
A local clock (either 98.304 MHz for S100, or 49.152 MHz for S50) is used for the synchronization of the TSB14AA1A
state machine within the PHY logic. The source of this clock must be placed as close as possible to PHY pin XI. The
greater the distance, the more the chance of interference from noise. The local clock reference signal is internally
divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information
and system clock (SCLK) sent to the link layer to synchronize the PHY-link interface.
The PHY-link interface (SCLK, LREQ, CTL[0,1], and D[0,1]) must be short (less than 4 inches if practical). The signals
driven across the PHY-link interface are at 3.3 V, but are at 49.152 MHz and should be treated with due care. These
signals should also be approximately the same length. The short distance is to minimize noise coupling from other
devices and signal loss due to resistance. They should be kept the same length to reduce propagation delay
mismatches across this synchronous interface. Refer to
Recommendations for PHY Layout
[10] for more information.
The TSB14AA1A requires an external 98.304-MHz reference oscillator input for S100 operation or 49.152-MHz for
S50 operation. Because of the frequencies involved (up to 49.152 MHz system clock at 100 Mbps) the etches
propagating the DATA and STRB signal in the backplane should be treated as transmission lines.
[6]
SN74FB2041A, 7
–
Bit TTL/BTL Transceiver
data sheet (SCBS172J)
(7] SN74BCT756,
Octal Buffer/Driver With Open-Collector Inputs
(SCBS056B)
[8]
TSB12LV01B/TSB14AA1A Reference Schematic (SLLS465)
[9]
TSB14AA1A/Transceivers Reference Schematic
()
[10]
Recommendations for PHY Layout
(SLLA020A)
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