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参数资料
| 型号： | TSB14C01HV |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的电机及电子学工程师联合会1394-1995背板收发器/仲裁者 |
| 文件页数： | 25/35页 |
| 文件大小： | 224K |
| 代理商： | TSB14C01HV |
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6
–
5
Table 6
–
9. Status Bit Description
BIT(s)
NAME
DESCRIPTION
0
Arbitration
Reset Gap
Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time. This time is defined
in the 1394
–
1995 standard
. This bit is used by the link in its busy/retry state machine.
1
Subaction Gap
Indicates that the PHY has detected that the bus has been idle for a subaction gap time. This time is defined in the
1394 standard.
2
Bus Reset
Indicates that the PHY has entered the bus reset state
3
Reserved
Reserved
4
–
7
Address
Holds the address of the PHY register whose contents are transferred to the link
8
–
15
IEEE Std 1394
–
1995,
IEEE Standard for a High Performance Serial Bus
Data
Indicates the data that is to be sent to the link
PHY
Ctl[0:1]
PHY
D[0:1]
00
00
01
01
00
00
S[0,1]
S[2,3]
01
00
00
S[14,15]
00
00
Figure 6
–
3. Status Transfer Timing
6.1.4
Transmit
When the link requests access to the serial bus through the LREQ terminal, the PHY arbitrates for access to the serial
bus. When the PHY wins the arbitration, it grants the bus to the link by asserting transmit on the CTL terminals for
one SCLK cycle, followed by idle for one cycle. After sampling the transmit state from the PHY, the link takes over
control of the interface by asserting either hold or transmit on the CTL terminals. The link asserts hold to keep
ownership of the bus while preparing data. The PHY asserts the data-on state on the serial bus during this time. When
it is ready to begin transmitting a packet, the link asserts transmit on the CTL terminals along with the first bits of the
packet. After sending the last bits of the packet, the link asserts either idle or hold on the CTL terminals for one cycle,
and then idle for one additional cycle before asserting those terminals to a high-impedance state.
The hold state indicates to the PHY that the link needs to send another packet without releasing the bus. The PHY
responds to this hold state by waiting the required minimum time and then asserting transmit as before. This function
is used after sending an acknowledgement if the link intends to send a unified response, during a single cycle. The
only requirement when sending multiples packet during bus ownership is that all packets must be transmitted at the
same speed, since the speed of the packet transmission is set before the first packet.
As noted above, when the link has finished sending the last packet for the current bus ownership, it releases the bus
by asserting idle on the CTL terminals for two SCLK cycles. The PHY begins asserting idle on the CTL terminals one
clock cycle after sampling the second idle from the link. Whenever the D and CTL links change ownership between
the PHY and the link, there is an extra clock period allowed so that both sides of the interface can operate on registered
versions of the interface signals, rather than having to respond to a CTL state on the next cycle.
It is not required that the link enter the hold state before sending the first packet when implementation permits the
link to be ready to transmit as soon as bus ownership is granted. The timing of a single packet transmit operation is
shown in Figure 6
–
4. In the diagram, D0
–
Dn are the data symbols of the packet, ZZ represents the high-impedance
state.
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