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参数资料
| 型号： | TSB14C01HV |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的电机及电子学工程师联合会1394-1995背板收发器/仲裁者 |
| 文件页数： | 22/35页 |
| 文件大小： | 224K |
| 代理商： | TSB14C01HV |
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6
–
2
Table 6
–
1. CTL Encoding When PHY Has Control of the Bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
No activity (this is the default mode)
0
1
Status
Status information is being sent from the PHY to the LLC.
1
0
Receive
An incoming packet is being sent from the PHY to the LLC.
1
1
Grant
The LLC has been given control of the bus to send an outgoing packet.
Table 6
–
2. CTL Encoding When LLC Has Control of the Bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
The LLC releases the bus (transmission has been completed).
0
1
Hold
The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to
be transmitted (concatenated) without arbitrating.
1
0
Transmit
An outgoing packet is being sent from the LLC to the PHY.
1
1
Reserved
Reserved
When the link needs to request the bus or access a register that is located in the TSB14AA1A PHY, a serial stream
of information is sent across the LREQ line. The length of the stream varies depending on whether the transfer is a
bus request, a read command, or a write command (see Table 6
–
3). Regardless of the type of transfer, a start bit of
1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the MSB,
and is transmitted first. The LREQ line is required to idle low (logic level 0).
Table 6
–
3. Request Bit Length
REQUEST TYPE
NUMBER OF BITS
Bus request (cable)
7
Bus request (backplane)
11
Read register request
9
Write register request
17
For a bus request in the cable environment, the length of the LREQ data stream is 7 bits as shown in Table 6
–
4.
Table 6
–
4. Bus Request for Cable Environment
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
1
–
3
Request type
Indicates the type of bus request (see Table 6
–
8 for the encoding of this field)
4
–
5
Request speed
Indicates the speed at which the PHY sends the packet for this request. This field has the same encoding as the
speed code from the first symbol of the receive packet. See Table 6
–
5 for the encoding of this field. This field can be
expanded to support data higher than 400 Mbit/s in the future.
6
Stop bit
Indicates the end of the transfer (always 0).
The 14AA1A will accept an LREQ transfer bus request in the backplane format. This request is 11 bits long and has
the format shown in Table 6
–
5. This is an optional feature of the backplane environment; it allows the priority of a
packet to be changed on a packet by packet basis. When using normal cable LREQs that are 7 bits long, the packet
will have the priority contained in the priority register of the TSB14AA1A. For this case to change the priority requires
software to change the value of the priority register inside the PHY.
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