参数资料
型号: TSB41BA3AIGGM
厂商: Texas Instruments, Inc.
英文描述: IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
中文描述: 的IEEE 1394b三端口电缆收发器/仲裁者
文件页数: 53/66页
文件大小: 895K
代理商: TSB41BA3AIGGM
SLLS618B JUNE 2004 REVISED AUGUST 2004
53
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
LLC service request (continued)
Table 27. Bus Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
14
Request type
Indicates the type of bus request. See Table 26.
5
Request format
Indicates the packet format to be used for packet transmission. See Table 28.
69
Request speed
Indicates the speed at which the link sends the data to the PHY. See Table 29 for the encoding of this field.
10
Stop bit
Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit may be omitted.
Table 28 shows the 1-bit request format field used in bus requests.
Table 28. Bus Request Format Encoding
LR5
DATA RATE
0
Link does not request either beta or legacy packet format for bus transmission
1
Link requests beta packet format for bus transmission
Table 29 shows the 4-bit request speed field used in bus requests.
Table 29. TBus Request Speed Encoding
LR6LR9
DATA RATE
0000
S100
0001
Reserved
0010
S200
0011
Reserved
0100
S400
0101
Reserved
0110
S800
All Others
Invalid
NOTE:
The TSB41BA3A accepts a bus request with an invalid speed code and processes the bus request
normally. However, during packet transmission for such a request, the TSB41BA3A ignores any
data presented by the LLC and transmits a null packet.
For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 30.
Table 30. Read Register Request
BIT(s)
NAME
DESCRIPTION
0
Start bit
Indicates the beginning of the transfer (always 1)
14
Request type
A 1010 indicates this is a read register request
58
Address
Identifies the address of the PHY register to be read
9
Stop bit
Indicates the end of the transfer (always 0)
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