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| 型号： | TSB41BA3AIGGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口电缆收发器/仲裁者 |
| 文件页数： | 55/66页 |
| 文件大小： | 895K |
| 代理商： | TSB41BA3AIGGM |
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SLLS618B JUNE 2004 REVISED AUGUST 2004
55
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
status transfer
A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. Two types
of status transfers may occur: bus status transfer and PHY status transfer. Bus status transfers send the
following status information: bus reset indications, subaction and arbitration reset gap indications, cycle start
indications, and PHY interface reset indications. PHY status transfers send the following information: PHY
interrupt indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link
interface error indications. The PHY uses a different mechanism to send the bus status transfer and the PHY
status transfer.
Bus status transfers use the CTL0CTL1 and D0D7 terminals to transfer status information. Bus status
transfers can occur during idle periods on the PHY-link interface or during packet reception. When the status
transfer occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that
each individual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only
one status bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset
on the serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all
packet transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the
link, and sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a
PHY interface reset operation, the PHY-link interface is reset on the following PCLK cycle.
Table 33 shows the definition of the bits during the bus status transfer and Figure 24 shows the timing.
Table 33. Status Bits
STATUS BIT
DESCRIPTION
D0
Bus reset
D1
Arbitration reset gap—Odd
D2
Arbitration reset gap—Even
D3
Cycle start—Odd
D4
Cycle start—Even
D5
Subaction gap
D6
PHY interface reset
D7
Reserved
D[0:7]
XX
ST
XX
CTL[0:1]
XX
01
XX
Status Bits
Figure 24. Bus Status Transfer Timing
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| TSB41BA3AIPFP | 功能描述:缓冲器和线路驱动器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| TSB41BA3APFP | 功能描述:缓冲器和线路驱动器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| TSB41BA3APFPG4 | 功能描述:1394 接口集成电路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB41BA3ATPFPEP | 功能描述:缓冲器和线路驱动器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| TSB41BA3B | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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