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| 型号： | TSB41BA3AIGGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| 中文描述： | 的IEEE 1394b三端口电缆收发器/仲裁者 |
| 文件页数： | 58/66页 |
| 文件大小： | 895K |
| 代理商： | TSB41BA3AIGGM |
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SLLS618B JUNE 2004 REVISED AUGUST 2004
58
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
receive (continued)
NOTE A: SPD = Speed code, see Table 36. d0–dn = Packet data. STATUS = status bits, see Table 33.
00
00
10
XX
dn
d0
SPD
(a)
(b)
FF (data-on)
D0–D7
CTL0, CTL1
PCLK
(c)
(d)
(e)
01
STATUS
10
FF
(data-on)
Figure 27. Normal Packet Reception Timing With Optional Bus Status Transfer
The sequence of events for a normal packet reception is as follows:
(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a
status transfer operation that is in progress so that the CTL lines may change from status to receive without
an intervening idle.
(b) Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles
preceding the speed-code. The PHY may optionally send a bus status transfer during the data-on indication
for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status
information on the D lines.
(c) Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive cycle
for which the D lines are not the data-on code. If the speed-code is invalid or indicates a speed higher that
that which the link is capable of handling, then the link must ignore the subsequent data.
(d) Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet data
on the D lines with receive on the CTL lines for the remainder of the receive operation.
(e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one idle cycle following a receive operation.
00
00
10
XX
(a)
(b)
(c)
FF (data-on)
D0–D7
CTL0, CTL1
PCLK
Figure 28. Null Packet Reception Timing
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相关代理商/技术参数 |
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|---|---|
| TSB41BA3AIPFP | 功能描述:缓冲器和线路驱动器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| TSB41BA3APFP | 功能描述:缓冲器和线路驱动器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| TSB41BA3APFPG4 | 功能描述:1394 接口集成电路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB41BA3ATPFPEP | 功能描述:缓冲器和线路驱动器 Mil Enh 3-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| TSB41BA3B | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
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