参数资料
型号: TSC21020F-20SBSL1
英文描述: IC CYCLONE III FPGA 40K 484UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 33/51页
文件大小: 763K
代理商: TSC21020F-20SBSL1
33
TSC21020F
4153F
AERO
06/03
Flags
Figure 7.
Flags
Parameter
20 MHz
Frequency
Dependency
(1)
Unit
Min
Max
Min
Max
t
SFI
High
(2)
FLAG3-0
IN
Setup before CLKIN
19
19 +
5DT/16
ns
t
HFI
(2)
FLAG3-0
IN
Hold after CLKIN High
0
12 +
7DT/16
ns
t
DWRFI
xWR Low
(2)
FLAG3-0
IN
Delay from xRD,
12
ns
t
HFIWR
Deasserted
(2)
FLAG3-0
IN
Hold after xRD, xWR
0
ns
t
DFO
FLAG3-0
OUT
Delay from CLKIN High
24
ns
t
HFO
FLAG3-0
OUT
Hold after CLKIN High
5
ns
t
DFOE
CLKIN High to FLAG3-0
OUT
Enable
(3)
1
ns
t
DFOD
CLKIN High to FLAG3-0
OUT
Disable
24
ns
Notes:
1. DT = t
CK
- 50 ns
2. Flag inputs meeting these setup and hold times will affect conditional operations in
the next instruction cycle. See the Hardware Configuration chapter of the
ADSP-
21020 User’s Manual from Analog Devices
for additional flag servicing information.
3. Guaranteed by design.
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