参数资料
型号: TSC21020F-20SBSL1
英文描述: IC CYCLONE III FPGA 40K 484UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 34/51页
文件大小: 763K
代理商: TSC21020F-20SBSL1
34
TSC21020F
4153F
AERO
06/03
Bus Request/Bus Grant
Figure 8.
Bus Request/Bus Grant
Parameter
20 MHz
Frequency
Dependency
(1)
Unit
Min
Max
Min
Max
t
HBR
BR Hold after CLKIN High
0
ns
t
SBR
BR Setup before CLKIN High
18
18+5DT/16
ns
t
DMDBGL
Memory Interface Disable
to BG Low
(2)
-2
ns
t
DME
CLKIN High to Memory
Interface Enable
25
25 + DT/2
ns
t
DBGL
CLKIN High to BG Low
22
ns
t
DBGH
CLKIN High to BG High
22
ns
Notes:
1. DT = t
CK
- 50 ns
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE,
DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Buses are not granted until completion of current memory access.
See the Memory Interface chapter of the
ADSP-21020 User’s Manual
from
Analog Devices for BG, BR cycle relationships.
2. Guaranteed by design.
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