参数资料
型号: TSC21020F-20SBSL1
英文描述: IC CYCLONE III FPGA 40K 484UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 46/51页
文件大小: 763K
代理商: TSC21020F-20SBSL1
46
TSC21020F
4153F
AERO
06/03
Target System
Requirements for Use of
EZ-ICE Emulator
The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG test access port of the
TSC21020F to monitor and control the target board processor during emulation. The
EZ-ICE probe requires that CLKIN, TMS, TCK, TRST, TDI, TDO, and GND be made
accessible on the target system via a 12-pin connector (pin strip header) such as that
shown in Figure 20. The EZ-ICE probe plugs directly onto this connector for chip-on-
board emulation; you must add this connector to your target board design if you intend
to use the ADSP-21020 EZ-ICE. Figure 21 shows the dimensions of the EZ-ICE probe;
be sure to allow enough space in your system to fit the probe onto the 12-pin connector.
Figure 20.
Target Board Connector for EZ-ICE Emulator (Jumpers In Place)
Figure 21.
EZ-ICE Probe
The 12-pin, 2-row pin strip header is keyed at the Pin 1 location - you must clip Pin 1 off
of the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin
spacing is 0.1 x 0.1 inches.
The tip of the pins must be at least 0.10 inch higher than the tallest component under the
probe to allow clearance for the bottom of the probe. Pin strip headers are available
from vendors such as 3M, McKenzie, and Samtec.
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