参数资料
型号: TSC21020F-20SBSL1
英文描述: IC CYCLONE III FPGA 40K 484UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 36/51页
文件大小: 763K
代理商: TSC21020F-20SBSL1
36
TSC21020F
4153F
AERO
06/03
Memory Read
Parameter
20 MHz
Frequency
Dependency
(1)
Unit
Min
Max
Min
Max
t
DAD
Address, Select to Data Valid
37
37 + DT
ns
t
DRLD
xRD Low to Data Valid
24
24 + 5DT/8
ns
t
HDA
Data Hold from Address,
Select
0
ns
t
HDRH
Data Hold from xRD High
-1
ns
t
DAAK
xACK Delay from Address
27
27 + 7DT/8
ns
t
DRAK
xACK Delay from xRD Low
15
15 + DT/2
ns
t
SAK
xACK Setup before CLKIN
High
14
14 + DT/4
ns
t
HAK
xACK Hold after CLKIN High
0
ns
t
DARL
Address, Select to xRD Low
8
8 + 3DT/8
ns
t
DAP
xPAGE Delay from Address,
Select
1
ns
t
DCKRL
CLKIN High to xRD Low
16
26
16 + DT/4
26 + DT/4
ns
t
RW
xRD Pulse Width
26
26 +
5DT/8
ns
t
RWR
xRD High to xRD, xWR Low
17
17 +
3DT/8
ns
Notes:
1. DT = t
CK
- 50 ns
2. x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0;
Select = PMS1-0, DMS3-0.
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