- 您现在的位置：买卖IC网 > PDF目录98302 > TSC2300IPAGRG4 (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQFP64 PDF资料下载
参数资料
| 型号： | TSC2300IPAGRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | GREEN, PLASTIC, TQFP-64 |
| 文件页数： | 59/83页 |
| 文件大小： | 1268K |
| 代理商： | TSC2300IPAGRG4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页当前第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
www.ti.com
TSC2300
SLAS372 — NOVEMBER 2002
Audio Data Converters
The TSC2300 includes a stereo 20-bit audio DAC and a mono 20-bit audio ADC. The DAC and ADC are both capable
of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz. The DAC and
ADC must operate at the same sampling rate.
When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to the I2S
bus clock. The MCLK can be 256/384/512 times the I2S LRCLK rate. An internal PLL takes any of these possible input
clocks and generates a digital clock for use by the internal circuitry of either 44.1 kHz x 512 = 22.5792 MHz (when 44.1
kHz submultiple sample-rates are selected) or 48 kHz x 512 = 24.576 MHz (when 48 kHz submultiple sample-rates are
selected). The user is required to set the MCLK bits (Bits[7:6], Reg 00h, Pg 2) to tell the part the ratio between MCLK
and the I2S LRCLK rate (there is no specific phase alignment requirement between MCLK and BCLK). The user is also
required to set the I2SFS bits (Bits[5:2], Reg 00h, Pg 2) to tell the part what sample rate is in use. When the user is
using either 44.1 kHz or 48-kHz sampling rates, and providing a 512 x Fs MCLK, the internal PLL is powered down, as
MCLK can be used directly to clock the internal circuitry. This reduces power consumption.
If the user wishes to change sampling rates, the data converters (both DAC’s and ADC) should be muted, then
powered down. The LRCLK and BCLK rates should then be changed. Next the user should write the appropriate
settings to the MCLK, I2SFS, and I2SFM bits, then power up the data converters. Finally, the data converters can be
un-muted.
Due to the wide supply range over which this part must operate, the audio does not operate on an internal reference
voltage. The common-mode voltage that the single-ended audio signals are referenced to is set by a divider between
the analog supplies and is given by 0.4 x AVDD. The reference voltages used by the audio codec must be provided as
inputs to the part at the Vref+/Vref- pins and are intended to be connected to the same voltage levels as AVDD and
AGND, respectively. Because of this arrangement, the voltages applied to AVDD, AGND, Vref+, and Vref- should be
kept as clean and noise-free as possible.
DAC Digital Volume Control
The DAC digital effects processing block implements a digital volume control that can be set through the SPI registers.
The volume level can be varied from 0 dB to -63.5 dB in 0.5-dB steps independently for each channel. The user can
mute each channel independently by setting the mute bits in the DAC volume control register (Reg 02h, Pg 2). There is
a soft-stepping algorithm included in this block, which only changes the actual volume every 20 s, either up or down,
until the desired volume is reached. This speed of soft-stepping can be slowed to once every 40 s through the
SSRTE bit (Bit 1, Reg 04h, Pg 2).
Because of this soft-stepping, the host does not know whether the DAC has actually been fully muted or not. This may
be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates.
In order to help with this situation, the part provides a flag back to the host via a read-only SPI register bit (Bit 0, Reg
04h, Pg 2) that alerts the host when the part has completed the soft-stepping, and the actual volume has reached the
desired volume level.
The part also includes functionality to detect when the user switches on or off the de-emphasis or bass-boost functions,
and to first soft-mute the DAC volume control, then change the operation of the digital effects processing, then
soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous changes in the
filtering. A similar algorithm is used when first powering up or down the DAC/ADC. The circuit begins operation at
power-up with the volume control muted, then soft-steps it up to the desired volume level slowly. At power-down, the
logic first soft-steps the volume down to a mute level, then powers down the circuitry.
Stereo DAC Overview
The stereo DAC consists of a digital block to implement digital interpolation filter, volume control, de-emphasis filter
and programmable digital effects/bass-boost filter for each channel. These are followed by a 5th-order single-bit digital
delta-sigma modulator, and switched capacitor analog reconstruction filter. The DAC has been designed to provide
enhanced performance at low sample rates through increased oversampling and image filtering, thereby keeping
quantization noise generated within the delta-sigma modulator and signal images strongly suppressed in the full audio
band of 20 Hz-20 kHz, even at low sample rates such as 8 kHz. This is realized by keeping the upsampled rate
approximately constant and changing the oversampling ratio as the input sample rate is reduced. For rates of
8/12/16/24/32/48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz, giving oversampling
ratios of 768/512/384/256/192/128, respectively. This ensures that quantization noise generated within the delta-sigma
modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for rates of
11.025/22.05/44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz, yielding
oversampling ratios of 512/256/128, respectively.
62
相关PDF资料 |
PDF描述 |
|---|---|
| TSC2301IPAGR | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TSC2301IPAG | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| TSC2301IGQZR | SPECIALTY CONSUMER CIRCUIT, PBGA120 |
| TSC2301IGQZ | SPECIALTY CONSUMER CIRCUIT, PBGA120 |
| TSC2301IZQZR | SPECIALTY CONSUMER CIRCUIT, PBGA120 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSC2301 | 制造商:TI 制造商全称:Texas Instruments 功能描述:PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH STEREO AUDIO CODEC |
| TSC2301EVM | 功能描述:触摸传感器开发工具 TSC2301 Eval Mod RoHS:否 制造商:Cypress Semiconductor 工具用于评估: 接口类型: 工作电压: 最大工作温度: |
| TSC2301IGQZ | 功能描述:触摸屏转换器和控制器 Prog 4-Wire w/20-Bit Stereo Audio Codec RoHS:否 制造商:Microchip Technology 类型:Resistive Touch Controllers 输入类型:3 Key 数据速率:140 SPS 分辨率:10 bit 接口类型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 电源电压:2.5 V to 5.25 V 电源电流:17 mA 工作温度:- 40 C to + 85 C 封装 / 箱体:SSOP-20 |
| TSC2301IGQZR | 功能描述:触摸屏转换器和控制器 Prog 4-Wire w/20-Bit Stereo Audio Codec RoHS:否 制造商:Microchip Technology 类型:Resistive Touch Controllers 输入类型:3 Key 数据速率:140 SPS 分辨率:10 bit 接口类型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 电源电压:2.5 V to 5.25 V 电源电流:17 mA 工作温度:- 40 C to + 85 C 封装 / 箱体:SSOP-20 |
| TSC2301IPAG | 功能描述:触摸屏转换器和控制器 Prog 4-Wire w/20-Bit Stereo Audio Codec RoHS:否 制造商:Microchip Technology 类型:Resistive Touch Controllers 输入类型:3 Key 数据速率:140 SPS 分辨率:10 bit 接口类型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 电源电压:2.5 V to 5.25 V 电源电流:17 mA 工作温度:- 40 C to + 85 C 封装 / 箱体:SSOP-20 |
发布紧急采购，3分钟左右您将得到回复。