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| 型号： | TSC2301IZQZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA120 |
| 封装： | GREEN, PLASTIC, VFBGA-120 |
| 文件页数： | 16/95页 |
| 文件大小： | 1322K |
| 代理商： | TSC2301IZQZR |
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DIGITAL INTERFACE
TSC2301 Communication Protocol
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
The TSC2301 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master
generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start
and synchronize transmissions.
A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the
slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts
out on the MISO pin to the master shift register.
When the POL pin of the TSC2301 is tied high (POL=1), the idle state of the serial clock for the TSC2301 is low,
which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). When the
POL pin of the TSC2301 is tied low (POL=0), the idle state of the serial clock is high, which corresponds to a
clock polarity setting of 1 (typical microprocessor SPI control bit CPOL = 1). The TSC2301 interface is designed
so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins
driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can
remain low between transmissions; however, the TSC2301 only interprets the first 16 bits transmitted after the
falling edge of SS as a command word, and the next 16 bits as a data word only if writing to a register. Reserved
register bits should be written to their default values (see Table 4).
The TSC2301 is entirely controlled by registers. Reading and writing these registers is accomplished by the use
of a 16-bit command, which is sent prior to the data for that register. The command is constructed as shown in
The command word begins with an R/W bit, which specifies the direction of data flow on the serial bus. The
following 4 bits specify the page of memory this command is directed to, as shown in Table 1. The next six bits
specify the register address on that page of memory to which the data is directed. The last five bits are reserved
for future use.
Table 1. Page Addressing
PG3
PG2
PG1
PG0
Page Addressed
0
1
0
1
0
2
0
1
reserved
0
1
0
reserved
0
1
0
1
reserved
0
1
0
reserved
0
1
reserved
1
0
reserved
1
0
1
reserved
1
0
1
0
reserved
1
0
1
reserved
1
0
reserved
1
0
1
reserved
1
0
reserved
1
reserved
To read all the first page of memory, for example, the host processor must send the TSC2301 the command
0x8000 - this specifies a read operation beginning at page 0, address 0. The processor can then start clocking
data out of the TSC2301. The TSC2301 automatically increments its address pointer to the end of the page; if
the host processor continues clocking data out past the end of a page, the TSC2301 simply sends back the
value 0xFFFF.
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