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参数资料
| 型号： | TSC2301IZQZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA120 |
| 封装： | GREEN, PLASTIC, VFBGA-120 |
| 文件页数： | 75/95页 |
| 文件大小： | 1322K |
| 代理商： | TSC2301IZQZR |
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TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Bit 15 — ADMUL
Left ADC Mute. This bit is used to mute the input to the left channel ADC volume control. The user can set this
bit to mute the ADC while retaining the previous gain setting in ADVL[6:0], so that the PGA returns to the
previous gain setting when ADMUL is cleared. When the ADMUL bit is set, the left ADC PGA soft-steps down to
its lowest level, then mutes. This procedure is used to reduce any audible artifacts (pops or clicks) during the
mute operation. This soft-stepping process is reversed when the ADMUL bit is cleared (unmute).
Table 38. Left ADC Mute
ADMUL
Description
0
Left channel ADC is active.
1
Left channel ADC is mute. (default)
Bits [14:8] — ADVL6- ADVL0
Left ADC Volume Control. These 7 bits control the gain setting of the left channel ADC volume control. This
volume control can be programmed from -40 dB to 20 dB in 0.5-dB steps. Full volume (+20 dB) corresponds to a
setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any value
lower than 07h engages the mute function described above. Volume control changes are always soft-stepped, as
described above. The default volume setting is 0 dB.
ADVL[6:0] = 1010111 (087d) = 0 dB (default)
ADVL[6:0] = 1111111 (127d) = +20 dB (Max)
ADVL[6:0] = 0000111 (007d) = -40 dB (Min)
ADVL[6:0] = 0d-6d = mute
Bit 7 — ADMUR
Right ADC Mute. This bit is used to mute the input to the right channel ADC. The user can set this bit to mute the
ADC while retaining the previous gain setting in ADVR[6:0], so that the PGA returns to the previous gain setting
when ADMUR is cleared. When the ADMUR bit is set, the right ADC PGA soft-steps down to its lowest level,
then mutes. This procedure is used to reduce any audible artifacts (pops or clicks) during the mute operation.
This soft-stepping process is reversed when the ADMUR bit is cleared (unmute).
Table 39. Right ADC Mute
ADMUR
Description
0
Right channel ADC is active.
1
Right channel ADC is mute. (default)
Bits [6:0] — ADVR6- ADVR0
Right ADC Volume Control. These 7 bits control the gain setting of the right channel ADC volume control PGA.
This volume control can be programmed from -40 dB to 20 dB in 0.5-dB steps. Full volume (20 dB) corresponds
to a setting of 7Fh. Unity gain (0 dB) corresponds to 57h. Full attenuation (-40 dB) corresponds to 07h. Any value
lower than 07h engages the mute function described above. Volume control changes are always soft-stepped, as
described above. The default volume setting is 0 dB.
ADVR[6:0] = 1010111 (087d) = 0 dB (default)
ADVR[6:0] = 1111111 (127d) = +20 dB (Max)
ADVR[6:0] = 0000111 (007d) = -40 dB (Min)
ADVR[6:0] = 0d-6d = mute
DAC VOLUME CONTROL REGISTER (Page 02, Address 02h)
The DAC volume control register controls the independent digital gain controls on the left and right channel audio
DAC's of the TSC2301. The gain of the DACs can be adjusted from -63.5 dB to 0 dB in 0.5-dB steps. The DAC
inputs can also be muted, so that all zeroes are sent to the DAC interpolation filters.
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