
TSC8051C1
Rev. D (14 Jan. 97)
23
MATRA MHS
Test Conditions
Unit
Max
Typ
Min
Parameter
Symbol
CIO
Capacitance of I/O Buffer
10
pF
fc = 1MHz, TA = 25
°C
ICC
Power Supply Current (8)
Active Mode 12MHz
Idle Mode
12MHz
8.5 (6)
2.6 (6)
17
8
mA
Vcc = 5.5V(1)
Vcc = 5.5V(2)
IPD
Power Down Current
5 (6)
30
A
Vcc = 2.0V to 5.5V(3)
Notes for DC Electrical Characteristics
1. ICC is measured with all output pins disconnected; XTAL1 driven
with TCLCH, TCHCL = 5 ns (see Figure 20. ), VIL = VSS +
0.5V, VIH = VCC – 0.5V; XTAL2 N.C.; EA = RST = Port 0 =
VCC. ICC would be slightly higher if a crystal oscillator used
(see Figure 17. ).
2. Idle ICC is measured with all output pins disconnected; XTAL1
driven with TCLCH, TCHCL = 5ns, VIL = VSS + 0.5V, VIH =
VCC–0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see
Figure 19. ).
3. Power Down ICC is measured with all output pins disconnected;
EA = PORT 0 = VCC; XTAL2 NC.; RST = VSS (see
Figure 19. ).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise
pulses to be superimposed on the VOLs of ALE and Ports 1 and
3. The noise is due to external bus capacitance discharging into
the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive
loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not
necessary.
5. The input threshold voltage of SCL and SDA (SIO1) meets the I2C
specification, so an input voltage below 0.3.VCC will be
recognised as a logic 0 while an input voltage above 0.7.VCC
will be recognised as a logic 1.
6. Typicals are based on a limited number of samples and are not
guaranteed. The values listed are at room temperature and 5V.
7. Under steady state (non–transient) conditions, IOL must be
externally limited as follows:
Maximum IOL per port pin:
10 mA
Maximum IOL per 8–bit port:
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total IOL for all output pins:
71 mA
If IOL exceeds the test condition, VOL may exceed the related
specification. Pins are not guaranteed to sink current greater than
the listed test conditions.
8. For other values, please contact your sales office.
RST
EA
XTAL2
XTAL1
VSS
VCC
ICC
(NC)
CLOCK SIGNAL
P0
VCC
All other pins are disconnected.
Figure 17. ICC Test Condition, Active Mode.
VCC
RST
EA
XTAL2
XTAL1
VSS
VCC
ICC
(NC)
CLOCK SIGNAL
P0
VCC
All other pins are disconnected.
Figure 18. ICC Test Condition, Idle Mode.
VCC
RST
EA
XTAL2
XTAL1
VSS
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
Figure 19. ICC Test Condition, Power Down Mode.