
TSC8051C1
Rev. D (14 Jan. 97)
15
MATRA MHS
7.2. Pulse Width Modulated Outputs
The
TSC8051C1
contains
twelve
pulse
width
modulated output channels (see Figure 10. ). These
channels generate pulses of programmable duty cycle
with an 8–bit resolution.
The 8–bit counter counts modulo 256 by default i.e.,
from 0 to 255 inclusive but can count modulo 254 i.e.,
from 0 to 253 inclusive by programming the bit 0 of the
PWMCON register. The counter clock is supplied by the
oscillator frequency. Thus, the repetition frequency
fpwm is constant and equals to the oscillator frequency
divided
by
256
or
254
(fpwm=46.875KHz
or
47.244KHz with a 12MHz oscillator). The 8–bit counter
is common to all PWM channels, its value is compared
to the contents of the twelve registers: PWM0 to
PWM11. Provided the content of each of these registers
is greater than the counter value, the corresponding
output is set low. If the contents of these registers are
equal to, or less than the counter value the output will be
high.
The pulse–width ratio is therefore defined by the
contents of these registers, and is in the range of 0 (all ‘0’
written to PWM register) to 255/256 or 1 (all ‘1’ written
to PWM register) and may be programmed in
increments of 1/256 or 1/254. When the 8–bit counter
counts modulo 254, it can never reach the value of the
PWM registers when they are loaded with FEh or FFh.
PWMx: Pulse Width Modulator x Register
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
When a compare register (PWM0 to PWM11) is loaded
with a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. All the PWM outputs are
open–drain outputs with standard current drive and
standard maximum voltage capability. When they are
disabled, eight of them (PWM0 to PWM7) are in high
impedance while the other four (PWM8 to PWM11) are
standard Port outputs with internal pullups.
PWM0 to PWM11 are write only registers. Their value
after reset is 00h.
PWM0 to PWM11 are using TSC8051C1 Special
Function Registers addresses as detailed in Table 4.
Table 4. PWM SFR register addresses
Channel
SFR address
PWM0
ECh
PWM1
EDh
PWM2
EEh
PWM3
EFh
PWM4
F4h
PWM5
F5h
PWM6
F6h
PWM7
F7h
PWM8
FCh
PWM9
FDh
PWM10
FEh
PWM11
FFh
Two 8–bit control registers: MXCR0 and MXCR1 are
used to enable or disable PWM outputs.
MXCR0 is used for PWM0 to PWM7. MXCR1 is used
for PWM8 to PWM11, these PWMs are multiplexed
with PORT 1 (see Table 5. )