参数资料
型号: TSC8051C1XXX-12IDD
元件分类: 8位微控制器
英文描述: 8-Bit Microcontroller for Digital Computer Monitors
中文描述: 8位数字的电脑显示器微控制器
文件页数: 31/31页
文件大小: 321K
代理商: TSC8051C1XXX-12IDD
TSC8051C1
Rev. D (14 Jan. 97)
9
MATRA MHS
Register
Content
PC
0000h
PCON
0XXX0000b
PSW
00h
PWM0–11
00h
PWMCON
XXXXXXX0b
S1CON
00h
S1DAT
00h
S1STA
F8h
SBUF
00h
SCON
00h
SOCR
00h
SP
07h
TCON
00h
TH0, TH1
00h
TL0, TL1
00h
TMOD
00h
The internal RAM is not affected by reset. At power–on
reset, the RAM content is indeterminate.
Watchdog
Reset
RST
Reset
Circuitry
Schmitt
Trigger
On–chip
resistor
RRST
Figure 5. On–Chip Reset Configuration.
An automatic reset can be obtained when VCC is turned
on by connecting the RST pin to VCC through a 1
F
capacitor providing the VCC setting time does not
exceed 1ms and the oscillator start–up time does not
exceed 10ms. This power–on reset circuit is shown in
Figure 6. When power comes on, the current drawn by
RST starts to charge the capacitor. The voltage at RST
is the difference between VCC and the capacitor
voltage, and decreases from VCC as the capacitor
charges. VRST must remain above the lower threshold of
the Schmitt trigger long enough to effect a complete
reset. The time required is the oscillator start–up time,
plus 2 machine cycles.
+
VSS
RST
VRST
RRST
VCC
TSC8051C1
VCC
1
mF
Figure 6. Power–on Reset Circuit
6.6. Oscillator Characteristics
XTAL1 and XTAL2 are respectively the input and
output of an inverting amplifier which is configured for
use as an on–chip oscillator. As shown in Figure 7. ,
either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source,
XTAL1 should be driven while XTAL2 is left
unconnected as shown in Figure 8.
There are no requirements on the duty cycle of the
external clock signal, since the input to the internal
clocking circuitry is through a divide–by–two flip–flop.
The minimum high and low times specified on the data
sheet must be observed however.
XTAL2
XTAL1
VSS
Figure 7. Crystal Oscillator
XTAL2
XTAL1
VSS
NC
EXTERNAL
OSCILLATOR
SIGNAL
Figure 8. External Drive Configuration
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