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参数资料
| 型号： | TSC8051C1XXX-12IDD |
| 元件分类： | 8位微控制器 |
| 英文描述： | 8-Bit Microcontroller for Digital Computer Monitors |
| 中文描述： | 8位数字的电脑显示器微控制器 |
| 文件页数： | 5/31页 |
| 文件大小： | 321K |
| 代理商： | TSC8051C1XXX-12IDD |
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TSC8051C1
Rev. D (14 Jan. 97)
13
MATRA MHS
Order
Source
Priority Within Level
1
INT0
(highest)
2
Timer 0
↑
3
INT1
4
Timer 1
5
SIO0
↓
6
SIO1
(lowest)
6.8.3. Interrupt Handling:
The interrupt flags are sampled at S5P2 of every
machine cycle. The samples are polled during the
following machine cycle. If one of the flags was in a set
condition at S5P2 of the previous machine cycle, the
polling cycle will find it and the interrupt system will
generate a LCALL to the appropriate service routine,
provided this hardware–generated LCALL is not
blocked by any of the following conditions:
1. An interrupt of higher or equal priority is
already in progress.
2. The current (polling) cycle is not the final
cycle in the execution of the instruction in progress.
3. The instruction in progress is RETI or any
access to the IE or IP SFR.
Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Note that
if an interrupt is active but not being responded to for one
of the above conditions, if the flag is not still active when
the blocking condition is removed, the denied interrupt
will not be serviced. In other words, the facts that the
interrupt flag was once active but not serviced is not
memorized. Every polling cycle is new.
The processor acknowledges an interrupt request by
executing
a
hardware–generated
LCALL
to
the
appropriate service routine. In some cases it also clears
the flag that generated the interrupt, and in other case it
does not. It clears the timer 0, timer 1, and external
interrupt flags. An external interrupt flag (IE0 or IE1) is
cleared only if it was transition–activated. All other
interrupt flags are not cleared by hardware and must be
cleared by the software. The LCALL pushes the
contents of the program counter onto the stack (but it
does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
vectored to, as listed below:
Source
Vector Address
IE0
0003h
TF0
000Bh
IE1
0013h
TF1
001Bh
RI + TI
0023h
SI
002Bh
Execution proceeds from the vector address until the
RETI instruction is encountered. The RETI instruction
clears the ‘priority level active’ flip–flop that was set
when this interrupt was acknowledged. It then pops two
bytes from the the top of the stack and reloads the
program counter with them. Execution of the interrupted
program continues from where it was interrupted.
相关PDF资料 |
PDF描述 |
|---|---|
| TSC8051C1XXX-12IDR | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-16CAR | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-16CBR | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-16CEB | 8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-16CED | 8-Bit Microcontroller for Digital Computer Monitors |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSC8051C1XXX-12IDR | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12IEB | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12IED | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12IER | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
| TSC8051C1XXX-12IGB | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:8-Bit Microcontroller for Digital Computer Monitors |
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