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参数资料
| 型号： | TSI206 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 6/28页 |
| 文件大小： | 286K |
| 代理商： | TSI206 |
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Tsi206 Primary Side Monitor with Inrush Control
Datasheet
- 14 -
Tundra Semiconductor Corporation
80C7000_MA001_01 April 2006
Choose the resistor divider values so that the
voltage at the VBATT pin is 2.39 V at the intended
OV detection level. OV detection is described more
fully in Primary OV and UV detection on page 14.
Seating
The card seating is determined by monitoring the
voltage on the SEAT pin. An external resistor
divider is used if necessary, depending on the
SEAT option used. The intermediate bus brick is not
turned on unless the SEAT pin is valid. A debounce
is provided, refer to Table 6 on page 16.
Dual comparators are used for the SEAT input,
which is internally floated at a voltage midway
between VDD and VSS. The SEAT status is
recognized as valid if the SEAT pin is pulled either
high or low. This allows the Tsi206 to detect either
a high or low SEAT connection, to suit different
possible application requirements.
If the seat function is not required, the SEAT pin can
be tied to VSS.
Primary OV and UV detection
The Tsi206 monitors the primary voltage using
comparators for undervoltage (UV) and overvoltage
(OV) conditions. The UV threshold is set by a
resistor divider connected into the UV pin. Internal
hysteresis is provided by switching in a current
source of 11
μA when a UV condition is present.
The UV threshold setpoint in the Tsi206 is very
precise, specified as 1.25 V ±10 mV.
Note: Tighter tolerance for UV shutdown is
available.
Contact
Tundra
Semiconductor
for
details
The UV condition is used by the Tsi206 to shut
down the brick. The resistor divider must be chosen
so that the voltage at the UV pin is exactly 1.25 V
when the input voltage is at the intended UV
shutdown level. Resistors with 0.1% tolerance are
recommended to maintain high accuracy.
An additional comparator with a threshold of 1.31 V
is connected to the UV pin and is used to generate
a
Brownout
signal.
The
Brownout
signal
is
transmitted to the secondary side controller through
the PI-Link interface as a warning. Because the
Brownout signal is derived from the same resistor
divider as the UV shutdown, the resistor tolerances
affect the two signals equally and guarantee that
Brownout is always detected before the UV
shutdown.
The OV threshold is detected by an internal
comparator connected to the voltage measurement
input (VBATT pin), with a value of 2.39 V. This
allows the OV setpoint to be chosen independently
of the UV setpoint.
Both UV and OV status is transmitted to the
secondary side through the PI-Link interface.
Note: When an OV condition is detected, the
Tsi205 does not normally disable the brick. As a
factory-programmed option, the brick can be shut
down when an OV condition is detected. Refer to
Table 9 on page 24 for details
Low input shutdown and restart
In most applications using battery backup, the low
input shutdown voltage (LISD) and the restart
voltage (LISDrec) are tightly specified. Overall
equipment specifications dictate the requirements
for each card. When using the Tsi206, the LISD
voltage at the card input is equal to the UV detection
threshold (VUVL) set by R3 and R9, plus the voltage
drop in the ORing diodes and input fuse. Choose
values of R3 and R9 that take into account the
voltage drop across the ORing diodes (D1 and D2
in Figure 1 on page 1), fuses and distribution wiring.
The restart voltage (LISDrec) is equal to the LISD
threshold plus the hysteresis. The hysteresis is set
by an internal 11
μA current sink connected to the
UV pin, as shown in Figure 6 on page 10. The
11
μA current sink is only active during the time
when a UV condition is present. The added current
flows through R3 and raises the UV detection level
(VUVH) by a voltage equal to (0.011 × R3) V, where
R3 is expressed in k
Ω. For example, if R3 is
301 k
Ω, the hysteresis is 3.31 V.
Using the suggested component values given in
Table 8 on page 23, the LISD is set to 37.08 V and
the LISDrec is set to 40.39 V nominal. Setpoint
accuracy for LISD is ±300 mV (plus the effect of the
tolerances of R3 and R9). Setpoint accuracy for
LISDrec is slightly reduced (±350 mV) due to the
tolerance of the 11
μA current sink (refer to Table
Primary side fuse status
The status of the primary input fuses is monitored
using two pins (FUSE_H, FUSE_L). A resistor
divider network is used to set the voltage on these
pins. The voltage levels are interpreted by the
Tsi206, and transmitted to the secondary side
through the PI-Link interface. A glitch filter is used
to avoid nuisance fault detection, refer to Table 6 on
page 16 for details.
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