SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
2.1.1
Video Input Switch Control
The TVP5160 decoder has two analog channels that accept up to 12 video inputs. The user can configure
the internal analog video switches via I2C. The 12 analog video inputs can be used for different input
configurations, some of which are:
12 CVBS video inputs
4 S-Video inputs and 2 CVBS inputs
3 YPbPr video inputs and 3 CVBS input
2 YPbPr video inputs, 2 S-Video inputs, and 2 CVBS inputs
The input selection is performed by the input select register at I2C subaddress 00h.
2.1.2
480p and 576p Component YPbPr
The TVP5160 decoder supports progressive component video inputs. The YPbPr inputs of the TVP5160
decoder may accept 480p or 576p progressive inputs. The Y channel is fed into one ADC while PbPr are
sampled alternatively by the other ADC.
2.1.3
Analog Input Clamping
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit
provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection
between bottom and mid clamp is performed automatically by the TVP5160 decoder.
2.1.4
Automatic Gain Control
The TVP5160 decoder uses two programmable gain amplifiers (PGAs); one per channel. The PGA can
scale a signal with a voltage input compliance of 0.5 VPP to 2.0 VPP to a full-scale, 11-bit, A/D output code
range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain
corresponds to a code 0x0 (2.0-VPP full-scale input, –6 dB gain) while maximum gain corresponds to code
0xF (0.5-VPP full scale, +6 dB gain). The TVP5160 decoder also has 12-bit fine gain controls for each
channel and applies independently to coarse gain controls. For composite video, the input video signal
amplitude may vary significantly from the nominal level of 1 VPP. The TVP5160 decoder can adjust its
PGA setting automatically: an automatic gain control (AGC) can be enabled and can adjust the signal
amplitude such that the maximum input range of the ADC is reached without clipping. Some nonstandard
video signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts
back gain to avoid clipping. If the AGC is on, then the TVP5160 decoder can read the gain currently being
used.
The TVP5160 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after Y/C
separation. The back-end AGC restores the optimum system gain whenever an amplitude reference, such
as the composite peak (which is only relevant before Y/C separation), forces the front-end AGC to set the
gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references: sync
height, color burst amplitude, composite peak, and luma peak.
The specific amplitude references being used by the front-end and back-end AGC algorithms can be
independently controlled using the AGC white peak processing register located at subaddress 74h. The
TVP5160 gain increment speed and gain increment delay can be controlled using the AGC increment
speed register located at subaddress 78h and the AGC increment delay register located at subaddress
79h, respectively.
2.1.5
Analog Video Output
Any one of the analog input signals is available at the analog video output pin. The signal at this pin must
be buffered by a source follower if it drives a 75-
Ω resister. The nominal output voltage is 2 VPP, and the
signal can drive a 75-
Ω line when buffered. The magnitude is maintained with a PGA in 16 steps
controlled by the TVP5160 decoder.
18
Functional Description
Copyright
2005–2011, Texas Instruments Incorporated