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SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
List of Figures
1-1
TVP5160 PNP-Package Terminal Diagram
..................................................................................
152-1
Analog Processors and A/D Converters
......................................................................................
182-2
Luminance Edge-Enhancer Peaking Block
...................................................................................
212-3
Peaking Filter Frequency Response NTSC/PAL ITU_R BT.601 Sampling
...............................................
212-4
Reference Clock Configuration
.................................................................................................
222-5
RTC Timing
.......................................................................................................................
232-6
Fast-Switches for SCART and Digital Overlay
...............................................................................
252-7
Vertical Synchronization Signals for 525-Line System
......................................................................
282-8
Vertical Synchronization Signals for 625-Line System
......................................................................
282-9
Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
..................................................................
292-10
Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
..................................................................
302-11
VS Position With Respect to HS for Interlaced Signals
.....................................................................
312-12
VS Position With Respect to HS for Progressive Signals
...................................................................
312-13
VBUS Access
.....................................................................................................................
332-14
Reset Timing
......................................................................................................................
373-1
Teletext Filter Function
..........................................................................................................
804-1
Application Example
.............................................................................................................
956-1
Clocks, Video Data, and Sync Timing
.......................................................................................
1006-2
I
2C Host Port Timing
............................................................................................................
1006-3
SDRAM Interface Timing
......................................................................................................
1016-4
TVP5160 Timing Relationship with K4S161622E-80 SDRAM
............................................................
1027-1
128-Pin PowerPAD Package
..................................................................................................
1054
List of Figures
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