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| 型号： | TVP5160PNP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封装： | GREEN, PLASTIC, HTQFP-128 |
| 文件页数： | 66/111页 |
| 文件大小： | 1400K |
| 代理商： | TVP5160PNP |
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SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
Table 3-42. Output Formatter Control 1
Subaddress
33h
Default
40h
7
6
5
4
3
2
1
0
Reserved
YCbCr code range
CbCr code
Reserved
Output format [2:0]
YCbCr output code range:
0 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)
1 = Extended coding range (Y, Cb, and Cr range from 4 to 1016) (default)
CbCr code format:
0 = Offset binary code (2s complement + 512) (default)
1 = Straight binary code (2s complement)
Output format [2:0]:
000 = 10-bit 4:2:2 (pixel
× 2 rate) with embedded syncs (ITU-R BT.656)
001 = 20-bit 4:2:2 (pixel rate) with discrete syncs
010 = Reserved
011 = 10-bit 4:2:2 with discrete syncs
100 = 20-bit 4:2:2 (pixel rate) with embedded syncs
101
–111 = Reserved
Note: 10-bit mode is also used for raw VBI output mode when bit 4 (VBI raw) in the luminance processing control 1 register at subaddress
06h is set.
Table 3-43. Output Formatter Control 2
Subaddress
34h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Data enable
"Blue" Screen Output [1:0]
Clock polarity
SCLK enable
Data enable: Y[9:0] and C[9:0] output enable
0 = Y[9:0] and C[9:0] high-impedance (default)
1 = Y [9:0] and C[9:0] active
"Blue" Screen Output [1:0]:
00 = Normal operation (default)
01 = "Blue" screen out when the TVP5160 decoder detects lost lock (with tuner input but not with VCR)
10 = Force "Blue" screen out
11 = Reserved
Fully programmable color of "blue screen" to support clean input/channel switching. When enabled, in case of lost lock, or when forced, the
decoder waits until the end of the current frame, then switches the output data to a programmable color. Once displaying the "blue screen",
the inputs and or RF channel can be switched without causing snow or noise to be displayed on the digital output data. Once the inputs
have settled, the "blue screen" can be disabled, and the decoder then waits until the end of the current video frame before re-enabling the
video stream data to the output ports.
Clock polarity:
0 = Data clocked out on the falling edge of SCLK (default)
1 = Data clocked out on the rising edge of SCLK
SCLK enable:
0 = SCLK outputs are high-impedance (default)
1 = SCLK outputs are enabled
58
Internal Control Registers
Copyright
2005–2011, Texas Instruments Incorporated
focus.ti.com: TVP5160
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