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| 型号： | TWR-ELEV |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 1/48页 |
| 文件大小： | 0K |
| 描述： | TOWER ELEVATOR BOARDS HARDWARE |
| 其它有关文件： | TWR-ELEV Dummy Schematic TWR-ELEV Functional Schematic |
| 产品培训模块： | MCF51CN Family - Ultimate Ethernet Solutions Tower System |
| 特色产品： | The Tower System |
| 标准包装： | 1 |
| 系列： | ColdFire® |
| 附件类型： | 2 个升降机板 |
| 适用于相关产品： | Freescale 电源塔系统 |
| 产品目录页面： | 734 (CN2011-ZH PDF) |
| 相关产品： | TWR-SER-ND - TOWER SERIAL I/O HARDWARE TWR-MCF51CN-ND - KIT TOWER BOARD TWR-MCF51CN-KIT-ND - KIT TOWER BOARD/SERIAL/ELEVATOR |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51CN128
Rev. 4, 5/2009
Freescale Semiconductor, Inc., 2009. All rights reserved.
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
MCF51CN128
80 LQFP
14 mm
× 14 mm
64 LQFP
10 mm
× 10 mm
48 QFN
7mm
× 7mm
The MCF51CN128 device is a low-cost, low-power,
high-performance 32-bit ColdFire V1 microcontroller (MCU)
featuring 10/100 BASE-T/TX fast ethernet controller (FEC),
media independent interface (MII) to connect an external
physical transceiver (PHY), and multi-function external bus
interface.
MCF51CN128 also has multiple communication interfaces
for various ethernet gateway applications. MCF51CN128 is
the first ColdFire V1 device to incorporate ethernet and
external bus interface along with new features to minimize
power consumption and increase functionality in low-power
modes.
The MCF51CN128 features the following functional units:
32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up
to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz
CPU from 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7
software interrupts
On-Chip Memory
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage
and temperature
– On-chip memory aliased to create a contiguous memory
space with off-chip memory
– Security circuitry to prevent unauthorized access to
Peripherals, RAM, and flash contents
Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet
controller with direct memory access (DMA); supports
half or full duplex; operation is limited to 3.0 V to 3.6 V
– MII—media independent interface to connect ethernet
controller to external PHY; includes output clock for
external PHY
External Bus
– Mini-FlexBus—Multi-function external bus interface;
supports up to 1 MB memories, gate-array logic, simple
slave device or glueless interfaces to standard
chip-selected asynchronous memories
– Programmable options: access time per chip select, burst
and burst-inhibited transfers per chip select, transfer
direction, and address setup and hold times
Power-Saving Modes
– Two low-power stop modes, one of which allows limited
use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows
full use of all peripherals; FEC can remain active and
conduct DMA transfers to RAM and assert an interrupt
to wake up the CPU upon completion
– Low-power run and wait modes allow peripherals to run
while the voltage regulator is in standby
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3
mode to provide accurate clock source to active
peripherals
– Low-power real-time counter for use in run, wait, and
stop modes with internal and external clock sources
–6
μs typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller
packages are automatically disabled for reduced current
consumption; no user interaction is needed
Clock Source Options
– Oscillator (XOSC) — Loop-control pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible
clock source module with either frequency-locked-loop
(FLL) or phase-lock loop (PLL) clock options. FLL can
be controlled by internal or external reference and
MCF51CN128 ColdFire
Microcontroller
Cover: MCF51CN128
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TWR-ELEV | 制造商:Freescale Semiconductor 功能描述:Tower System - Elevator Boards |
| TWR-FRAM | 功能描述:存储器 IC 开发工具 Freescale Tower FRAM Daughter Card RoHS:否 制造商:STMicroelectronics 产品:Reference Boards 工具用于评估:M24LR64-R 存储容量:64 kbit 存储类型:EEPROM 工作电源电压:1.8 V to 5.5 V |
| TWR-HW | 功能描述:WIRELESS RELAY 120/277 HARD WIRE 制造商:thomas research products 系列:ZenNet 零件状态:过期 配件类型:无线继电器 配套使用产品/相关产品:* 标准包装:1 |
| TWR-IND-IO | 功能描述:界面开发工具 IND CTRL Tower IO RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| TWR-K20D50M | 功能描述:开发板和工具包 - ARM PK20DX128VLH5 EvBrd RoHS:否 制造商:Arduino 产品:Development Boards 工具用于评估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口类型:DAC, ICSP, JTAG, UART, USB 工作电源电压:3.3 V |
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