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参数资料
| 型号： | UPD750004GBA-XXX-3BS-MTX |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件页数： | 4/86页 |
| 文件大小： | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
10
Data Sheet U10738EJ3V2DS
3.2
NON-PORT PINS
Notes 1. The circle (
) indicates the Schmitt trigger input.
2. With a noise eliminator/asynchronously selectable
3. Asynchronous
B
F
M
B
Function
Inputs external event pulse to the timer/event
counter
Timer/event counter output
Timer counter output
Clock output
Arbitrary frequency output (for buzzer output or
system clock trimming)
Serial clock I/O
Serial data output
Serial data bus I/O
Serial data input
Serial data bus I/O
Edge detection vectored interrupt input (both
rising and falling edges are detected)
Rising edge detection testable input
Falling edge detection testable input
Crystal/ceramic connection pin for main system
clock generation. When external clock signal is
used, it is applied to X1, and its reverse phase
signal is applied to X2.
Crystal connection pin for subsystem clock
generation. When external clock signal is used, it
is applied to XT1, and it reverse phase signal is
applied to XT2.
XT1 can be used as a 1-bit input (test).
System reset input (active low)
Internally connected. (To be connected directly to
VDD)
Positive power supply
Ground potential
Input/
output
Input
Output
I/O
Input
I/O
Input
-
Input
-
Input
-
When reset
Input
-
Edge detection vectored interrupt input
(detection edge selectable). A noise eliminator
can be selected when INT0/P10 is used.
Shared
pin
P13
P20
P21
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60 - P63
P70 - P73
-
Note 3
Note 2
Note 3
I/O circuit
typeNote 1
-C
E-B
-A
-B
-C
-A
-
B
Pin name
TI0
PTO0
PTO1
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0 - KR3
KR4 - KR7
X1
X2
XT1
XT2
RESET
IC
VDD
VSS
F
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