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参数资料
| 型号： | UPD750004GBA-XXX-3BS-MTX |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件页数： | 59/86页 |
| 文件大小： | 626K |
| 代理商： | UPD750004GBA-XXX-3BS-MTX |
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PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
60
Data Sheet U10738EJ3V2DS
AC CHARACTERISTICS (TA = -40 to +85
°C, VDD = 2.2 to 5.5 V)
CPU clock cycle
timeNote 1 (minimum
instruction execution time
= 1 machine cycle)
TI0 input frequency
TI0 input high/low level
width
Interrupt input high/low
level width
RESET low level width
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
Remark The shaded portion is guaranteed only when the
external clock is used.
When external
clock is used
IM02 = 0
IM02 = 1
Notes 1. The cycle time of the CPU clock (
Φ)
(minimum instruction execution time) de-
pends on the frequency of connected reso-
nator (and external clock), the system
clock control register (SCC), and the proc-
essor clock control register (PCC).
The figure on the right side shows the
cycle time tCY characteristics for the sup-
ply voltage VDD during main system clock
operation.
2. This value becomes 2tCY or 128/fX accord-
ing to the setting of the interrupt mode
register (IM0).
When ceramic
or crystal is
used
Operated
by main
system
clock
pulse
tCY
fTI
tTIH,
tTIL
tINTH,
tINTL
tRSL
Conditions
Min.
Typ.
Max.
Unit
0.67
64
s
0.85
64
s
0.67
64
s
0.95
64
s
Operated by subsystem clock pulse
114
122
125
s
VDD = 2.7 to 5.5 V
0
1.0
MHz
0
275
kHz
VDD = 2.7 to 5.5 V
0.48
s
1.8
s
INT0
Note 2
s
10
s
INT1, INT2, and INT4
10
s
KR0 to KR7
10
s
10
s
Parameter
Symbol
0123456
0.5
1
2
3
4
5
6
60
64
tCY vs. VDD
(Main system clock in operation)
Operation guaranteed
range
1.8
2.2 2.7
5.5
0.67
0.95
0.85
Cycle
time
t
CY
[
s]
Power supply voltage VDD [V]
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