参数资料
型号: UPD78F9202MA-CAC-A
厂商: Renesas Electronics America
文件页数: 144/158页
文件大小: 0K
描述: MCU 8BIT 4KB FLASH 128B RAM
标准包装: 400
系列: 78K0S/Kx1+
核心处理器: 78K0S
芯体尺寸: 8-位
速度: 10MHz
外围设备: LVD,POR,PWM,WDT
输入/输出数: 7
程序存储器容量: 4KB(4K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 10-LSSOP(0.225",5.72mm 宽)
包装: 托盘
CHAPTER 5 CLOCK GENERATORS
User’s Manual U18172EJ3V0UD
84
(2) Crystal/ceramic oscillator (
μPD78F920x only)
If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected
and the accuracy of processing is improved because the frequency deviation is small, as compared with high-
speed internal oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator (
μPD78F920x Only)
VDD
Crystal/ceramic
oscillator clock
PCC = 02H, PPCC = 02H
(a)
(b)
(c)
H
RESET
System clock
Internal reset
CPU clock
Option byte is read.
System clock is selected.
(Operation stops
Note 1)
Clock oscillation
stabilization
timeNote 2
Notes 1. Operation stop time is 276
μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to
CHAPTER 15 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is
released is selected by the oscillation stabilization time select register (OSTS).
(a) The internal reset signal is generated by the power-on clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) After high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is
selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
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