参数资料
型号: UPD78F9202MA-CAC-A
厂商: Renesas Electronics America
文件页数: 94/158页
文件大小: 0K
描述: MCU 8BIT 4KB FLASH 128B RAM
标准包装: 400
系列: 78K0S/Kx1+
核心处理器: 78K0S
芯体尺寸: 8-位
速度: 10MHz
外围设备: LVD,POR,PWM,WDT
输入/输出数: 7
程序存储器容量: 4KB(4K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 10-LSSOP(0.225",5.72mm 宽)
包装: 托盘
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18172EJ3V0UD
38
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area (Other than the internal high-speed RAM area cannot be set as the stack
area).
Figure 3-9. Stack Pointer Configuration
0
15
SP14
SP15
SP
SP13 SP12 SP11 SP10
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.
Caution 1.
Since reset signal generation makes the SP contents undefined, be sure to initialize the
SP before using the stack memory.
2.
Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits can
be actually set.
0FF00H is in the SFR area, not the high-speed RAM area, so it was converted to 0FB00H
that is in the high-speed RAM area.
When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to become
0FAFFH, but that value is not in the high-speed RAM area, so it is converted to 0FEFFH,
which is the same value as when 0FF00H is set to the stack pointer.
Figure 3-10. Data to Be Saved to Stack Memory
Interrupt
PSW
PC15 to PC8
PC7 to PC0
Lower half
register pairs
SP
SP _ 2
CALL, CALLT
instructions
PUSH rp
instruction
SP _ 1
SP
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP _ 3
Upper half
register pairs
Figure 3-11. Data to Be Restored from Stack Memory
RETI instruction
PSW
PC15 to PC8
PC7 to PC0
Lower half
register pairs
RET instruction
POP rp
instruction
SP
PC7 to PC0
Upper half
register pairs
SP + 1
SP
SP + 2
SP
SP + 1
SP
SP + 2
SP
SP + 1
SP + 2
SP
SP + 3
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