参数资料
型号: UPD78F9202MA-CAC-A
厂商: Renesas Electronics America
文件页数: 3/158页
文件大小: 0K
描述: MCU 8BIT 4KB FLASH 128B RAM
标准包装: 400
系列: 78K0S/Kx1+
核心处理器: 78K0S
芯体尺寸: 8-位
速度: 10MHz
外围设备: LVD,POR,PWM,WDT
输入/输出数: 7
程序存储器容量: 4KB(4K x 8)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 10-LSSOP(0.225",5.72mm 宽)
包装: 托盘
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (
μPD78F920x ONLY)
User’s Manual U18172EJ3V0UD
98
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F
set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot
pulse output operation enable/disable, and output trigger of one-shot pulse by software.
TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the value of TOC00 to 00H.
Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FF63H
After reset: 00H
R/W
Symbol
7
<6>
<5>
4
<3>
<2>
1
<0>
TOC00
0
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger control via software
0
No one-shot pulse output trigger
1
One-shot pulse output trigger
OSPE00
One-shot pulse output operation control
0
Successive pulse output mode
1
One-shot pulse output mode
Note
TOC004
Timer output F/F control using match of CR010 and TM00
0
Disables inversion operation
1
Enables inversion operation
LVS00
LVR00
Timer output F/F status setting
0
No change
0
1
Timer output F/F reset (0)
1
0
Timer output F/F set (1)
1
Setting prohibited
TOC001
Timer output F/F control using match of CR000 and TM00
0
Disables inversion operation
1
Enables inversion operation
TOE00
Timer output control
0
Disables output (output fixed to level 0)
1
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match
between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.
Cautions 1. Timer operation must be stopped before setting other than OSPT00.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required, when OSPT00 is set to 1 successively.
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