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参数资料
| 型号： | UPSD3213B-24U1T |
| 厂商： | 意法半导体 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| 中文描述： | 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的 |
| 文件页数： | 114/176页 |
| 文件大小： | 1081K |
| 代理商： | UPSD3213B-24U1T |
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PSD323X
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Unlock Bypass.
The Unlock Bypass instructions
allow the system to program bytes to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass Mode is entered
by firstinitiating twoUnlock cycles. Thisis followed
by a third WRITE cycle containing the Unlock By-
pass code, 20h (as shown in Table 85).
The Flash memory then enters theUnlock Bypass
Mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h. The sec-
ond cycle contains theprogram addressand data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programming.
During the Unlock Bypass Mode, only the Unlock
Bypass Program and Unlock Bypass Reset Flash
instructions are valid.
To exit the Unlock Bypass Mode, the system must
issue thetwo-cycle UnlockBypass ResetFlash in-
struction. The first cycle must contain the data
90h; thesecondcycle thedata00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.
Erasing Flash Memory
Flash Bulk Erase.
The Flash Bulk Erase instruc-
tion uses six WRITE operations followed by a
READ operation of the status register, as de-
scribed in Table 85. If any byte of the Bulk Erase
instruction is wrong, the Bulk Erase instruction
aborts and the device is reset to the READ Flash
memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled “Pro-
gramming Flash Memory,” page 112. The Error
Flag Bit (DQ5) returns a ’1’ if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).
It is not necessary to program the memory with
00h because the PSD MODULE automatically
does this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase.
The Sector Erase instruc-
tion uses six WRITE operations, as described in
Table 85. Additional Flash Sector Erase codes
and Flash memory sector addresses can be writ-
ten subsequently to erase other Flash memory
sectors in parallel, without further coded cycles, if
the additional bytes are transmitted in a shorter
time than the time-out period of about 100
μ
s. The
input of a new Sector Erase code restarts the time-
out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is ’1,’ the time-out period
has expired and the embedded algorithm is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase
instructions abort the cycle that is currently in
progress, and reset the device to READ Mode.
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7), as detailed in the section entitled “Pro-
gramming Flash Memory,” page 112.
During execution of the Erase cycle, the Flash
memory accepts only RESET and Suspend Sec-
tor Erase instructions. Erasure of one Flash mem-
ory sector may be suspended, in order to read
data from another Flash memory sector, and then
resumed.
Suspend Sector Erase.
When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend the cycle by writ-
ing 0B0h to any address when an appropriate
Sector Select (FS0-FS7or CSBOOT0-CSBOOT3)
is High. (See Table 85). This allows reading of
data from another Flash memory sector after the
Erase cycle has been suspended. Suspend Sec-
tor Erase is accepted only during an Erase cycle
and defaults to READ Mode. A Suspend Sector
Erase instruction executed during an Erase time-
out period, in addition to suspending the Erase cy-
cle, terminates the time out period.
TheToggle FlagBit (DQ6)stops toggling when the
internal logic is suspended. The status of this bit
must be monitored at an address within the Flash
memory sector being erased. The Toggle Flag Bit
(DQ6) stops toggling between 0.1
μ
s and 15
μ
s af-
ter the Suspend Sector Erase instruction hasbeen
executed. The Flash memory is then automatically
set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
– Attempting to read from a Flash memory sector
that was being erased outputs invalid data.
– Reading from a Flash sector that was not being
erased is valid.
– The Flash memory cannotbe programmed, and
only responds to Resume Sector Erase and
Reset Flash instructions (READ is an operation
and is allowed).
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相关代理商/技术参数 |
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| UPSD3213B-24U6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213B-24U6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3213B-40T1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3213B-40T1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| UPSD3213B-40T6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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