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参数资料
| 型号： | UT65L168(I) |
| 英文描述： | Pseudo Low Power SRAM |
| 中文描述： | 伪低功率SRAM |
| 文件页数： | 13/13页 |
| 文件大小： | 175K |
| 代理商： | UT65L168(I) |
UTRON
UT65L1616(E)/UT65L1616(I)
Rev. 1.1
1M X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC.
P80080
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
9
WRITE CYCLE 3 ( LB , UB controlled, ZZ =VIH)
t WC
t AW
t CW (2)
t AS (3)
t WR (4)
t WP (1)
t BW
t DW
t DH
Data Valid
Address
CE
WE
LB , UB
Dout
Din
High-Z
Notes :
1. A write occurs during the overlap (tWP) of low WE and CE . A write begins when CE goes low and WE goes low with
asserting LB or UB for single byte operation or simultaneously asserting LB and UB for double byte operation. A write ends
at the earliest transition when CE goes high and WE goes high. The tWP is measured from the beginning of write to the end of
write.
2. tCW is measured from the CE going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. The tWR applied in case a write ends as CE or WE going high.
5. Don’t access device with cycle timing shorter than tRC (tWC) for continuous periods > 40us.
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