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参数资料
| 型号： | UT65L168(I) |
| 英文描述： | Pseudo Low Power SRAM |
| 中文描述： | 伪低功率SRAM |
| 文件页数： | 9/13页 |
| 文件大小： | 175K |
| 代理商： | UT65L168(I) |
UTRON
UT65L1616(E)/UT65L1616(I)
Rev. 1.1
1M X 16 BITS LOW POWER PSEUDO SRAM
UTRON TECHNOLOGY INC.
P80080
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
AC TEST CONDITIONS
Input Pulse Levels
0.2V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL = 30pF+1TTL, IOH/IOL = -1mA / 2mA
AC ELECTRICAL CHARACTERISTICS (VCC =2.5V~3.3V)
(1) READ CYCLE
UT65L1616-60
UT65L1616-70
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
tRC
60
40k
70
40k
ns
Address Access Time
tAA
-
60
-
70
ns
Chip enable to output
tACE
-
60
-
70
ns
Output Enable to Valid Output
tOE
-
25
-
25
ns
Chip enable to Low-Z output
tCLZ
10
-
10
-
ns
Output Enable to Low-Z Output
tOLZ
5
-
5
-
ns
Chip Disable to High-Z Output
tCHZ
0
5
0
5
ns
Output Disable to High-Z Output
tOHZ
0
5
0
5
ns
Output Hold from Address Change
tOH
5
-
5
-
ns
LB , UB Access Time
tBA
-
60
-
70
ns
LB , UB Disable to High-Z Output
tBHZ
0
5
0
5
ns
LB , UB Enable to Low-Z Output
tBLZ
10
-
10
-
ns
(2) WRITE CYCLE
UT65L1616-60
UT65L1616-70
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Write Cycle Time
tWC
60
40k
70
40k
ns
Address Valid to End of Write
tAW
50
-
60
-
ns
Chip enable to End of Write
tCW
50
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Write Pulse Width
tWP
50
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Data to Write Time Overlap
tDW
20
-
20
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End Write to Output Low-Z
tOW
5
-
5
-
ns
Write to Output High Z
tWHZ
0
5
0
5
ns
LB , UB Valid to End of Write
tBW
50
-
60
-
ns
(3) PAGE MODE CYCLE
UT65V168-60
UT65V168-70
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Page Mode Cycle Time
tPC
25
-
25
-
ns
Page Mode Address Access Time
tPAA
-
25
-
25
ns
Maximum Cycle Time
tMRC
-
40k
-
40k
ns
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