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V58C2256324SA Rev. 1.4 August 2007
ProMOS TECHNOLOGIES
V58C2256324SA
Write with Autoprecharge (WRITEA)
If A8 is high when a Write command is issued, the Write with Auto-Precharge function is performed. The internal precharge begins after
the write recovery time tWR and tRAS(min) are satisfied.
If a Write with Auto Precharge command is initiated, the DDR SDRAM automatically enters the precharge operation at the first rising
edge of CLK after the last valid edge of DQS (completion of the burst) plus the write recovery time tWR. Once the precharge operation
has started, the bank cannot be reactivated and the new command can not be asserted until the Precharge time (tRP) has been satisfied.
If tRAS(min) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied.
Write Burst with Auto Precharge
Note: tWR starts at the first rising edge of clock after the last valid edge of the 4 DQSx.
Table
Concurrent Write Auto Precharge Support
When Write with Auto Precharge is asserted, new commands can be asserted at T3.. T8 as shown in Table .
An Interrupt of a running WRITE burst with Auto Precharge i.e. at T3 to the same bank with another WRITE+AP command is allowed
as long as the burst is running, it will extend the begin of the internal Precharge operation to the last WRITE+AP command.
Interrupts of a running WRITE burst with Auto Precharge i.e. at T3 are not allowed when doing concurrent WRITE s to another active
bank. Consecutive WRITE or WRITE+AP bursts (T4.. T7) to other open banks are possible. ACTIVATE or PRECHARGE commands to
another bank are always possible while a WRITE with Auto Precharge operation is in progress.
Asserted
Command
For same Bank
For different Bank
T3
T4
T5
T6
T7
T8
T3
T4
T5
T6
T7
WRITE
NONONONONO
NO
YES
WRITE+AP
YES
NO
YES
READ
NO
YES
READ+AP
NONONONONO
NO
NONONO
NO
YES
ACTIVATE
NO
YES
PRECHARGE
NONONONONO
NO
YES
WRITE A
+ AP
CLK
BANK A
ACTIVATE
Command
NOP
Burst length = 4
DQSx
DQx
D-in
0
D-in
1
D-in
2
D-in
3
Begin of
Auto Precharge
BL / 2
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
t RAS(min)
t RP
t WR