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参数资料
| 型号： | W19B320BBBH |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | FLASH 3V PROM, PDSO48 |
| 封装： | TSOP-48 |
| 文件页数： | 2/51页 |
| 文件大小： | 649K |
| 代理商： | W19B320BBBH |
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W19B320BT/B DATASHEET
Publication Release Date:Dec, 22, 2008
- 10 -
Revisionv A5
To verify the protect/unprotect status of the Security Sector; follow the algorithm show in
Security Sector Protect Verify.
The Security Sector protection must be used with caution, since there is no procedure available for
unprotect the Security Sector area and none of the bits in the Security Sector memory space can be
modified in any ways.
6.1.13 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during VDD power-up and power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses, which is less than 5 ns (typical) on #OE, #CE or #WE, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
Power-Up Write Inhibit
During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
6.2
Command Definitions
The device operation can be initiated by writing specific address and data commands or sequences into
the command register. The device will be reset to reading array data when writing incorrect address
and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
6.2.1 Reading Array Data
After device power-up, it is automatically set to reading array data. There is no commands are required
to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, each bank is
ready to read array data.
The system must initiate the reset command to return a bank to read mode if DQ5 goes high during an
active program or erase operation, or the bank is in the AUTOSELECT mode. See Reset Command
section and Requirements for Reading Array Data in the Device Bus Operations section for more
information.
6.2.2 Reset Command
The banks will be to the read mode when writing the reset command. For this command, the address
bits are Don’t Care.
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PDF描述 |
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| W19B320STT9F | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| W19L320STT9L | 2M X 16 FLASH 3.3V PROM, 90 ns, PDSO48 |
| W19B324MBT9G | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| W19B324MTB9L | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W19B320BB-H | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
| W19B320BB-M | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
| W19B320BT | 制造商:WINBOND 制造商全称:Winbond 功能描述:32Mbit, 2.7~3.6-volt single bank CMOS flash memory |
| W19B320BT-H | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
| W19B320BT-M | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
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