- 您现在的位置：买卖IC网 > PDF目录68423 > W19B320BBBH (WINBOND ELECTRONICS CORP) FLASH 3V PROM, PDSO48 PDF资料下载
参数资料
| 型号： | W19B320BBBH |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | FLASH 3V PROM, PDSO48 |
| 封装： | TSOP-48 |
| 文件页数： | 6/51页 |
| 文件大小： | 649K |
| 代理商： | W19B320BBBH |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
W19B320BT/B DATASHEET
Publication Release Date:Dec, 22, 2008
- 14 -
Revisionv A5
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. Once the Embedded Program algorithm has completed that the device outputs
the data programmed to DQ7. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active
for about 1
μs, and then that bank returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase
algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors
selected for erasure must be provided to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100
μs, and then the bank returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within
a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change
from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output,
the system may read the status or valid data. Even if the device has completed the program or erase
operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on
DQ0-DQ7 will appear on successive read cycles.
6.3.2 RY/#BY: Ready/#Busy
The
RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The
RY/#BY status is valid after the rising edge of the final #WE pulse in the
command sequence. Since
RY/#BY is an open-drain output, several RY/#BY pins can be tied together in
parallel with a pull-up resistor to VDD.
When the output is low (Busy), the device is actively erasing or programming. When the output is high
(Ready), the device is in the read mode or the standby mode.
6.3.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid after the rising edge of the final
#WE pulse in the
command sequence (before the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either
#OE or #CE to control the read cycles. Once the operation has
completed, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for about 100
μs, and then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors which are protected.
If a program address falls within a protected sector, DQ6 toggles for about 1
μs after the program
command sequence is written, and then returns to reading array data.
6.3.4 Reading Toggle Bits DQ6/DQ2
Whenever the system initially starts to read toggle bit status, it must read DQ0-DQ7 at least twice in a row to
determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the
toggle bit after the first read. While after the second read, the system would compare the new value of the
相关PDF资料 |
PDF描述 |
|---|---|
| W19B320STT9F | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| W19L320STT9L | 2M X 16 FLASH 3.3V PROM, 90 ns, PDSO48 |
| W19B324MBT9G | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| W19B324MTB9L | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| W19B322MBT9G | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W19B320BB-H | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
| W19B320BB-M | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
| W19B320BT | 制造商:WINBOND 制造商全称:Winbond 功能描述:32Mbit, 2.7~3.6-volt single bank CMOS flash memory |
| W19B320BT-H | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
| W19B320BT-M | 制造商:WINBOND 制造商全称:Winbond 功能描述:2.7~3.6-volt write (program and erase) operations |
发布紧急采购，3分钟左右您将得到回复。