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参数资料
| 型号： | W224BX |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 2/17页 |
| 文件大小： | 349K |
| 代理商： | W224BX |
W224B
2
Pin Definitions
Pin Name
CPU0,
CPU_F1:2
PCI1:6, PCI_F
Pin No.
52, 50, 49
Pin
Type
Pin Description
CPU Clock Outputs:
Frequency is set by the FS0:1 inputs or through serial input
interface. The CPU0 output is gated by the CLK_STOP# input.
33MHz PCI Outputs:
Except for the PCI_F output, these outputs are gated by
the PCI_STOP# input.
APIC Output:
2.5V fixed 33.33-MHz clock. This output is synchronous to the
CPU clock.
SDRAM Output Clocks:
3.3V outputs running at either 100 MHz or 133 MHz
depending on the setting of FS0:1 inputs. DCLK is a free-running clock.
66-MHz Clock Outputs:
3.3V fixed 66-MHz clock.
O
13, 15, 16, 18,
19, 20, 12
55, 54
O
APIC0:1
O
SDRAM0:5,
DCLK
3V66_0:1,
3V66_AGP
USB
DOT
REF
VCH_CLK
46, 45, 43, 42,
40, 39, 38
7, 8, 9
O
O
25
26
1
36
O
O
O
O
USB Clock Output:
3.3V fixed 48-MHz, non-spread spectrum USB clock output.
Dot Clock Output:
3.3V fixed 48-MHz, non-spread spectrum signal.
Reference Clock:
3.3V 14.318-MHz clock output.
Video Control Hub Clock Output:
3.3V selectable 48-MHz non-spread spec-
trum or 66.67-MHz spread spectrum clock output.
Power Down Control:
3.3V LVTTL-compatible input that places the device in
power-down mode when held LOW.
CPU Output Control:
3.3V LVTTL-compatible input that stops only the CPU0
clock. Output remains in the LOW state.
PCI Output Control:
3.3V LVTTL-compatible input that stops PCI1:6 clocks.
Output remains in the LOW state.
Test Mode Control:
3.3V LVTTL-compatible input to place the device into test
mode.
Frequency Selection Input:
3.3V LVTTL-compatible input used to select the
CPU and SDRAM frequencies. See Frequency Table.
SMBus Clock Input:
Clock pin for SMBus circuitry.
SMBus Data Input:
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection:
Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
3.3V Power Connection:
Power supply for core logic, PLL circuitry, SDRAM
outputs buffers, PCI output buffers, reference output buffers and 48-MHz output
buffers. Connect to 3.3V.
PWR_DWN#
32
I
CPU_STP#
34
I
PCI_STP#
11
I
TEST#
33
I
FS0:1
28, 29
I
SCLK
SDATA
X1
31
30
3
I
I/O
I
X2
4
O
VDD_REF,
VDD_3V66
VDD _PCI,
VDD_48MHz,
VDD_VCH,
VDD_SDRAM,
VDD_SDRAM
VDD_APIC,
VDD_CPU
GND_REF,
GND_3V66,
GND_PCI,
GND_PCI,
GND_48MHz,
GND_SDRAM.
GND_SDRAM.
GND_CPU,
GND_APIC
2, 10, 17, 27, 35,
37, 44
P
51, 53
P
2.5V Power Connection:
Power supply for APIC and CPU output buffers. Con-
nect to 2.5V.
Ground Connection:
Connect all ground pins to the common system ground
plane.
5, 6, 14, 21, 24,
41, 47, 48, 56
G
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