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参数资料
| 型号： | W224BX |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 6/17页 |
| 文件大小： | 349K |
| 代理商： | W224BX |
W224B
6
W224 provides one PWR_DWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
Notes:
7.
8.
9.
10. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Once the PWR_DWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W224.
Table 6. 133 MHz/SDRAM Test Mode Group Timing Relationships and Tolerance
CPU to
SDRAM
3.75 ns
500 ps
CPU to 3V66
0.0 ns
500 ps
SDRAM to
3V66
3.75 ns
500 ps
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
1.0 ns
USB& DOT
Async
N/A
Offset
Tolerance
Table 7. W224 Maximum Allowed Current
W224
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
= 2.625V
All static inputs = V
DDQ3
or V
SS
< 1 mA
Max. 3.3V supply consumption
Max. discrete cap loads
V
= 3.465V
All static inputs = V
DDQ3
or V
SS
< 1 mA
Powerdown Mode
(PWR_DWN# = 0)
Full Active 66 MHz
FS1:0 = 00 (PWR_DWN# =1)
Full Active 100 MHz
FS1:0 = 01 (PWR_DWN# =1)
Full Active 133 MHz
FS1:0 = 11 (PWR_DWN# =1)
60 mA
160 mA
75 mA
160 mA
90 mA
160 mA
Figure 5. W224 PWR_DWN# Timing Diagram
[7, 8, 9, 10]
1
2
Center
0ns
25ns
50ns
75ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
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