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参数资料
| 型号： | W224BX |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC |
| 中文描述： | CPU系统时钟发生器|采用TSSOP | 56PIN |塑料 |
| 文件页数： | 3/17页 |
| 文件大小： | 349K |
| 代理商： | W224BX |
W224B
3
Overview
The W224 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel
architec-
ture platform using graphics integrated core logic.
CPU/SDRAM Frequency Selection
CPU output frequency is selected through pins 28 and 29. For
CPU/SDRAM frequency programming information, refer to
Table 2
Alternatively, frequency selections are available
through the serial data interface.
.
Notes:
1.
2.
3.
4.
5.
6.
Provided for board-level “bed of nails” testing.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
Required for DC output impedance verification.
“Normal” mode of operation.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
VDD_CORE
22
P
3.3V Analog Power Connection:
Power supply for core logic, PLL circuitry. Con-
nect to 3.3V.
Analog Ground Connection:
Ground for core logic, PLL circuitry.
GND_CORE
23
G
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
Table 2. Frequency Select Truth Table
TEST#
FS1
0
X
0
X
1
0
1
0
1
1
1
1
FS0
0
1
0
1
0
1
CPU
Hi-Z
TCLK/2
66 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Hi-Z
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
Hi-Z
TCLK/3
66 MHz
66 MHz
66 MHz
66 MHz
PCI
Hi-Z
TCLK/6
33 MHz
33 MHz
33 MHz
33 MHz
48MHz
Hi-Z
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
Hi-Z
TCLK
APIC
Hi-Z
TCLK/6
33 MHz
33 MHz
33 MHz
33 MHz
Notes
1
2, 3
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
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