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参数资料
| 型号： | W250-03 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 1/12页 |
| 文件大小： | 120K |
| 代理商： | W250-03 |
PRELIMINARY
FTG for VIA Apollo Pro-266
W250-03
Cypress Semiconductor Corporation
Document #: 38-07254 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
3
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
System frequency synthesizer for VIA Apollo Pro-266
Supports Intel Pentium II and Pentium III class pro-
cessor
Three copies of CPU output
Nine copies of PCI output
One 48-MHz output for USB
One 24-MHz or 48-MHz output for SIO
Two buffered reference outputs
Three copies of APIC output
Supports frequencies up to 200 MHz
SMBus interface for programming
Power management control inputs
Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-Cycle Jitter:................................................250 ps
CPU to CPU Output Skew:...............................................175 ps
PCI Cycle to Cycle Jitter:..................................................500 ps
PCI to PCI Output Skew:..................................................500 ps
Intel and Pentium are registered trademarks of Intel Corporation.
Table 1. Pin Selectable Frequency
Input Address
FS4
FS3
FS2
FS1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
CPU,
(MHz)
200.0
190.0
180.0
170.0
166.0
AGP
66.6
63.3
60.0
56.7
83.0
PCI
(MHz)
33.3
31.7
30.0
28.3
41.5
Spread
Spectrum
OFF
OFF
OFF
OFF
OFF
FS0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
160.0
150.0
145.0
140.0
136.0
130.0
124.0
66.6
100.0
118.0
133.3
66.8
100.2
115.0
133.6
66.8
100.2
110.0
133.6
105.0
90.0
85.0
78.0
66.6
100.0
75.0
133.3
80.0
75.0
72.5
70.0
68.0
65.0
62.0
66.6
66.6
78.7
66.6
66.8
66.8
76.7
66.8
66.8
66.8
73.3
66.8
70.0
60.0
56.7
78.0
66.6
66.6
75.0
66.6
40.0
37.5
36.3
35.0
34.0
32.5
31.0
33.3
33.3
39.3
33.3
33.4
33.4
38.3
33.4
33.4
33.4
36.7
33.4
35.0
30.0
28.3
39.0
33.3
33.3
37.5
33.3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
+0.25%
+0.25%
OFF
+0.25%
+0.5%
+0.5%
OFF
+0.5%
OFF
OFF
OFF
OFF
-0.5%
-0.5%
OFF
-0.5%
Table 1. Pin Selectable Frequency
(continued)
Input Address
FS4
FS3
FS2
FS1
FS0
CPU,
(MHz)
AGP
PCI
(MHz)
Spread
Spectrum
Block Diagram
Pin Configuration
Note:
1.
Signals marked with
‘
*
’
have internal pull-up resistors.
[1]
VDD_REF
REF0
REF1/FS4
OSC
PLL Ref Freq
DIV
PLL 1
X2
X1
VDD_PCI
Stop
PCI1:8
48MHz/FS3
24_48MHz/FS2
PLL2
÷
2,3,4
PWR_DWN#
VDD_48 MHz
SMBus
Logic
SDATA
SCLK
CPU1:3
VDD_REF
GND_REF
X1
X2
VDD_48 MHz
FS3*/48 MHz
FS2*/24_48 MHz
GND_48 MHz
PCI_F
PCI1
PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*FS1
*FS0
AGP0
VDD_AGP
W
REF0
REF1/FS4*
VDD_APIC
APIC0
APIC1
GND_APIC
APIC2
VDD_CPU
GND_CPU
CPU1
CPU2
VDD_CPU
GND_CPU
CPU3
CPU_STOP#*
PCI_STOP#*
PWR_DWN#*
VDD_CORE
GND_CORE
SDATA
SCLK
AGP2
AGP1
GND_AGP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
÷
2
CStop
PCI_STOP#
PCI_F
APIC0:2
VDD_AGP
AGP0:2
VDD_CPU
DIV
FS0:1
CPU_STOP#
VDD_APIC
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