W250-03
PRELIMINARY
Document #: 38-07254 Rev. *A
Page 4 of 12
Writing Data Bytes
Each bit in Data Bytes 0
–
7 controls a particular device function
except for the
“
reserved
”
bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7.
Table 4
gives the bit formats for registers located in Data
Bytes 0
–
7.
Table 5
details additional frequency selections that are avail-
able through the serial data interface.
Table 4. Data Bytes 0
–
7 Serial Configuration Map
Affected Pin
Pin No.
Pin Name
Data Byte 0
7
--
--
6
--
--
5
--
--
4
--
--
3
--
--
2
--
--
1
--
--
0
--
--
Data Byte 1
7
--
--
6
--
--
5
--
--
4
--
--
3
35
CPU3
2
38
CPU2
1
39
CPU1
0
42
APIC2
Data Byte 2
7
20
PCI8
6
18
PCI7
5
17
PCI6
4
16
PCI5
3
14
PCI4
2
13
PCI3
1
11
PCI2
0
10
PCI1
Data Byte 3
7
--
--
6
--
SEL_48MHz
Bit(s)
Control Function
Bit Control
Default
0
1
(Reserved)
SEL_2
SEL_1
SEL_0
Hardware/Software Frequency Select
SEL_4
SEL_3
--
--
0
0
0
0
0
1
0
0
See
Table 5
See
Table 5
See
Table 5
Hardware
Software
See
Table 5
See
Table 5
Normal
Three-stated
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
--
--
--
--
--
--
0
0
0
0
1
1
1
1
Low
Low
Low
Low
Active
Active
Active
Active
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
1
(Reserved)
SEL 48MHz as the output frequency for
24_48MHz
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
--
--
0
0
24 MHz
48 MHz
5
4
3
2
1
6
7
9
48MHz
24_48MHz
PCI_F
AGP2
AGP1
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
1
1
1
1
1
27
26