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参数资料
| 型号： | W250-03 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 时钟和缓冲器 |
| 文件页数： | 3/12页 |
| 文件大小： | 120K |
| 代理商： | W250-03 |
W250-03
PRELIMINARY
Document #: 38-07254 Rev. *A
Page 3 of 12
Serial Data Interface
The serial data interface can be used to configure internal reg-
ister settings that control particular device functions. Upon
power-up, the W250-03 initializes with default register set-
tings, therefore the use of this serial data interface is optional.
The serial interface is write-only (to the clock chip) and is the
dedicated function of device pins SDATA and SCLOCK. In
motherboard applications, SDATA and SCLOCK are typically
driven by two logic outputs of the chipset. Clock device register
changes are normally made upon system initialization, if any
are required. The interface can also be used during system
operation for power management functions.
Table 2
summa-
rizes the control functions of the serial data interface.
Operation
Data is written to the W250-03 in eleven bytes of eight bits
each. Bytes are written in the order shown in
Table 3
.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Description
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change un-
der normal system operation.
For EMI reduction.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Spread Spectrum
Enabling
Output Three-state
(Reserved)
Enables or disables spread spectrum clocking.
Puts clock output into a high impedance state.
Reserved function for future device revision or pro-
duction device testing.
Production PCB testing.
No user application. Register bit must be writ-
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W250-03 to accept the bits in Data Bytes 0
–
6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W250-03 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W250-03, therefore bit values are ignored (
“
don
’
t care
”
).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the W250-03, therefore bit values are ignored (
“
don
’
t care
”
).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
The data bits in Data Bytes 0
–
7 set internal W250-03 registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to
Table 4
, Data Byte Serial Configuration
Map.
2
Command
Code
Don
’
t Care
3
Byte Count
Don
’
t Care
4
5
6
7
8
9
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to
Table 4
10
11
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