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参数资料
| 型号： | W25Q64CVSSIG |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.208 INCH, GREEN, SOIC-8 |
| 文件页数： | 18/79页 |
| 文件大小： | 1086K |
| 代理商： | W25Q64CVSSIG |
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W25Q64CV
Publication Release Date: April 01, 2011
- 25 -
Revision C
(IO
1)
7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status
Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO
pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7. The Status
Register bits are shown in Figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0,
SRP1, QE, LB[3:1], CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 7. The instruction is completed by driving /CS high.
/CS
CLK
DI
(IO
0)
DO
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (05h or 35h)
High Impedance
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Status Register 1 or 2 out
**
= MSB
*
Figure 7. Read Status Register Instruction Sequence Diagram
7.2.9 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2,
LB1, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-
volatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in
Figure 3 and described in 7.1.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction
code “01h”, and then writing the status register data byte as illustrated in Figure 8.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1 can not be changed from “1” to “0” because of the OTP protection for
these bits. Upon power off, the volatile Status Register bit values will be lost, and the non-volatile Status
Register bit values will be restored when power on again.
相关PDF资料 |
PDF描述 |
|---|---|
| W25Q64CVZPAP | 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| WMS128K8C-25CQE | 128K X 8 STANDARD SRAM, 25 ns, CDIP32 |
| WMF512K8X-150DEC5 | 512K X 8 FLASH 5V PROM, 150 ns, CDSO32 |
| WME128K8X-200DEC | 128K X 8 EEPROM 5V, 200 ns, CDSO32 |
| WMF512K8X-70FEM5 | 512K X 8 FLASH 5V PROM, 70 ns, CDFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W25Q64CVSSIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCAG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCAP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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