参数资料
型号: W25Q64CVSSIG
厂商: WINBOND ELECTRONICS CORP
元件分类: PROM
英文描述: 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
封装: 0.208 INCH, GREEN, SOIC-8
文件页数: 41/79页
文件大小: 1086K
代理商: W25Q64CVSSIG
W25Q64CV
- 46 -
DO
(IO
1)
7.2.26 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 24.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress,
the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY
bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection
table).
/CS
CLK
DI
(IO
0)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Instruction (C7h/60h)
High Impedance
Figure 24. Chip Erase Instruction Sequence Diagram
相关PDF资料
PDF描述
W25Q64CVZPAP 64M X 1 SPI BUS SERIAL EEPROM, PDSO8
WMS128K8C-25CQE 128K X 8 STANDARD SRAM, 25 ns, CDIP32
WMF512K8X-150DEC5 512K X 8 FLASH 5V PROM, 150 ns, CDSO32
WME128K8X-200DEC 128K X 8 EEPROM 5V, 200 ns, CDSO32
WMF512K8X-70FEM5 512K X 8 FLASH 5V PROM, 70 ns, CDFP32
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