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参数资料
| 型号： | W25Q64CVSSIG |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.208 INCH, GREEN, SOIC-8 |
| 文件页数： | 35/79页 |
| 文件大小： | 1086K |
| 代理商： | W25Q64CVSSIG |
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W25Q64CV
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7.2.19 Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad
I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random
Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place)
to be performed on serial flash devices.
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit
SPI instruction code (BBh, EBh, E7h or E3h) is needed or not for the next command. When M5-4 = (1,0),
the next command will be treated same as the current Dual/Quad I/O Read command without needing the
8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all
commands can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be
used.
7.2.20 Continuous Read Mode Reset (FFh or FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in Figure 18.
/CS
CLK
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
3
4
5
Don't Care
6
7
8
9
10
11
12
13
14
15
Mode Bit Reset
for Quad I/O (FFh)
Mode 0
Mode 3
Mode Bit Reset
for Dual I/O (FFFFh)
Don't Care
Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O
Since W25Q64CV does not have a hardware Reset pin, so if the controller resets while W25Q64CV is set
to Continuous Mode Read, the W25Q64CV will not recognize any initial standard SPI instructions from the
controller. To address this possibility, it is recommended to issue a Continuous Read Mode Reset
instruction as the first instruction after a system Reset. Doing so will release the device from the
Continuous Read Mode and allow Standard SPI instructions to be recognized.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are
needed to shift in instruction “FFFFh”.
相关PDF资料 |
PDF描述 |
|---|---|
| W25Q64CVZPAP | 64M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| WMS128K8C-25CQE | 128K X 8 STANDARD SRAM, 25 ns, CDIP32 |
| WMF512K8X-150DEC5 | 512K X 8 FLASH 5V PROM, 150 ns, CDSO32 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W25Q64CVSSIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCAG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCAP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CVTCIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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