参数资料
型号: W25Q64FVSFIG
厂商: Winbond Electronics
文件页数: 50/89页
文件大小: 0K
描述: IC SPI FLASH 64MBIT 16SOIC
标准包装: 44
系列: SpiFlash®
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 64M(8M x 8)
速度: 80MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
W25Q64FV
6.2.25
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “ 60h ” . The Chip Erase instruction sequence is shown in Figure 24.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of t CE (See AC Characteristics). While the Chip Erase cycle is in progress,
the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The
BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to
accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory
Protection table).
/CS
/CS
CLK
Mode 3
Mode 0
0
1
Mode 3
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 3
In structio n
CLK
Mode 0
Mode 0
C7h/60h
DI
(IO 0 )
Instruction (C7h/60h)
IO 0
IO 1
DO
High Impedance
IO 2
(IO 1 )
IO 3
Figure 24. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)
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