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参数资料
| 型号： | W39V040AQZ |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 512K X 8 FLASH 3.3V PROM, 11 ns, PDSO32 |
| 封装： | LEAD FREE, 8 X 14 MM, STSOP-32 |
| 文件页数： | 3/39页 |
| 文件大小： | 440K |
| 代理商： | W39V040AQZ |
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W39V040A
Publication Release Date: June 21, 2005
- 11 -
Revision A6
6.14.3 Standard LPC Memory Cycle Definition
FIELD
NO. OF
CLOCKS
DESCRIPTION
Start
1
"0000b" appears on LPC bus to indicate the initial
Cycle Type &
Dir
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
TAR
2
Turned Around Time
Addr.
8
Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
The addresses transfer most significant nibble first and least significant nibble
last.
(i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)
Sync.
N
Synchronous to add wait state.
"0000b" means Ready, "0101b" means Short
Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.
Data
2
Data Phase for Memory Cycle. The data transfer least significant nibble first and
most significant nibble last.
(i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)
6.15 Table of Command Definition
COMMAND
NO. OF
1ST
CYCLE
2ND
CYCLE
3RD
CYCLE
4TH
CYCLE
5TH
CYCLE
6TH
CYCLE
DESCRIPTION
CYCLES
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
ADDR.
DATA
Read
1
AIN
DOUT
Chip Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
Sector Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
SA
(3)
30
Page Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
PA
(4)
50
Byte Program
4
5555
AA
2AAA
55
5555
A0
AIN
DIN
Top Boot Block
Lockout –
64K/16KByte
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40/70
Product ID Entry
3
5555
AA
2AAA
55
5555
90
Product ID Exit
(1)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
(1)
1
XXXX
F0
Notes:
1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]
3. Address Format: A14
A0 (Hex); Data Format: DQ7 DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W39V040B | 制造商:WINBOND 制造商全称:Winbond 功能描述:W39V040B |
| W39V040B_07 | 制造商:WINBOND 制造商全称:Winbond 功能描述:512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE |
| W39V040BP | 制造商:WINBOND 制造商全称:Winbond 功能描述:W39V040B |
| W39V040BPZ | 制造商:WINBOND 制造商全称:Winbond 功能描述:W39V040B |
| W39V040BQ | 制造商:WINBOND 制造商全称:Winbond 功能描述:W39V040B |
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