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参数资料
| 型号： | W3HG2128M72AEF665F2MBG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 16/18页 |
| 文件大小： | 348K |
| 代理商： | W3HG2128M72AEF665F2MBG |
W3HG2128M72AEF-Fx
June 2007
Rev. 3
ADVANCED*
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
support when the high speed link is down. The SMBus
address straps located on the FBDIMM connector are
used to set the unique ID.
CHANNEL LATENCY
FBDIMM channel latency is measured from the time
a read request is driven on the FBDIMM channel pins
to the time when the first 16 bytes (2nd chunk) of read
completion data is sampled by the memory controller.
When not using variable READ latency, the latency
for a specific FBDIMM on a channel is always equal
to the latency for any other FBDIMM on that channel.
However, the latency for each FBDIMM in a specific
configuration with some number of FBDIMMs installed
may not be equal to the latency for each FBDIMM in a
configuration with some different number of FBDIMMs
installed. As more FBDIMMs are added to the channel,
additional latency is required to read from each FBDIMM
on the channel.
Because the channel is based on point-to-point
interconnection of buffer components between
FBDIMMs, memory requests are required to travel
through N-1 buffers before reaching the Nth buffer. The
result is that a four-FBDIMM channel configuration will
have greater idle READ latency compared to a one
FBDIMM channel configuration.
The variable READ latency capability can be used to
reduce latency for FBDIMMs closer to the host. The
idle latencies listed in this section are representative of
what might be achieved in typical AMB designs. Actual
implementations with latencies less than the values
listed will have higher application performance and vice
versa.
PEAK THEORETICAL THROUGHPUT
An FBDIMM channel transfers READ completion data
on the northbound data connection; 144 bits of data
are transferred for every northbound data frame. This
matches the 18-byte data transfer of an ECC DDR2
SDRAM device in a single DDR2 SDRAM command
clock. A DDR2 SDRAM device burst of eight from a
single channel, or burst of four from two lock-step
channels, provides a total of 72 bytes of data (64 bytes
plus 8 bytes ECC). The AMB frame rate matches the
DDR2 SDRAM command clock because of the fixed
6:1 ratio of the FBDIMM channel clock to the DDR2
SDRAM command clock. Therefore, the northbound
data connection will exhibit the same peak theoretical
throughput as a single DDR2 SDRAM channel. For
example, when using DDR2 533 componente, the peak
theoretical bandwidth of the northbound data connection
is 4.267 GB/sec.
Write data is transferred on the southbound command
and data connection, via Command + Wdata frames; 72
bits of data are transferred per frame. Two Command
+ Wdata frames match the 18-byte data transfer of
an ECC DDR2 SDRAM in a single DDR2 SDRAM
command clock.
A DDR2 SDRAM burst of eight transfers from a single
channel, or a burst of four from two lock-step channels,
provides a total of 72 bytes of data (64 bytes plus 8
bytes ECC). When the FBDIMM frame rate matches
the DDR2 SDRAM command clock, the southbound
command and data connection will exhibit one half the
peak theoretical throughput of a single DDR2 SDRAM
channel. For example, when using DDR2-533 SDRAMs,
the peak theoretical bandwidth of the southbound
command and data connection is 2.133 GB/sec.
The total peak-theoretical throughput for a single
FBDIMM channel is defined as the sum of the
peak-theoretical throughput of the northbound data
connection and the southbound command and data
connection. When the FBDIMM frame rate matches the
DDR2 SDRAM command clock, it equals 1.5 times the
peak-theoretical throughput of a single DDR2 SDRAM
channel. For example, when using DDR2-533 SDRAMs,
the peak theoretical throughput of a DDR2-533 channel
would be 4.267 GB/sec, while the peak theoretical
throughput of an FBDIMM-533 channel would be 6.4
GB/sec.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER534AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER665AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER806AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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